UT62L5128BS-100LI データシートの表示（PDF） - Utron Technology Inc

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UT62L5128BS-100LI

512K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.7

UT62L5128(I)

512K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)

t WC

Address

t AW

CE

t CW

t AS

t WR

t WP

WE

Dout

Din

t WHZ

(4)

High-Z

t DW

t OW

(4)

t DH

Data Valid

WRITE CYCLE 2 ( CE Controlled) (1,2,5)

Address

t WC

CE

t AS

t AW

t CW

t WR

WE

t WP

Dout

t WHZ

High-Z

t DW

t DH

Din

Data Valid

Notes :

1. WE or CE must be HIGH during all address transitions.

2. A write occurs during the overlap of a low CE and a low WE .

3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and

data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.

6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

6

P80052

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