AD6640 データシートの表示（PDF） - Analog Devices
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AD6640 Datasheet PDF : 24 Pages
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AD6640–SPECIFICATIONS
DC SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40؇C, TMAX = +85؇C, unless otherwise noted.)
Parameter
Test
AD6640AST
Temp
Level
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
+25°C
I
Full
VI
Full
VI
+25°C
I
Full
V
GUARANTEED
–10
+3.5
+10
–10
+4.0
+10
–1.0
± 0.5
+1.5
± 1.25
mV
% FS
LSB
LSB
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
V
50
ppm/°C
Full
V
100
ppm/°C
POWER SUPPLY REJECTION RATIO (PSRR)
Full
V
REFERENCE OUT (VREF)2
ANALOG INPUTS (AIN, AIN)3
Analog Input Common-Mode Range4
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
Full
V
Full
V
Full
V
Full
IV
0.7
+25°C
V
± 0.5
2.4
VREF ± 0.05
2.0
0.9
1.1
1.5
mV/V
V
V
V p-p
kΩ
pF
POWER SUPPLY
Supply Voltage
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
Full
VI
4.75
5.0
5.25
V
Full
VI
3.0
3.3
5.25
V
Full
VI
Full
VI
135
160
mA
10
20
mA
POWER CONSUMPTION
Full
VI
710
865
mW
NOTES
1ENCODE = 20 MSPS
2If VREF is used to provide a dc offset to other circuits, it should first be buffered.
3The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 V. The input signals should be 180 degrees out of phase to produce
a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 17 for more detail).
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (AVCC = 5 V, DVCC = 3.3 V; TMIN = –40؇C, TMAX = +85؇C, unless otherwise noted.)
Parameter
Test
AD6640AST
Temp
Level
Min
Typ
Max
Unit
LOGIC INPUTS (ENCODE, ENCODE)1
ENCODE Input Common-Mode Range2
Differential Input Voltage
Single-Ended ENCODE
Logic Compatibility3
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
Full
IV
Full
IV
Full
VI
Full
VI
Full
VI
Full
VI
+25°C
V
0.2
0.4
2.0
0
+500
–400
TTL/CMOS
+650
–320
2.5
2.2
10
5.0
0.8
+800
–200
V
V p-p
V p-p
V
V
µA
µA
pF
LOGIC OUTPUTS (D11–D0)4
Logic Compatibility
Logic “1” Voltage (DVCC = 3.3 V)
Logic “0” Voltage (DVCC = 3.3 V)
Logic “1” Voltage (DVCC = 5.0 V)
Logic “0” Voltage (DVCC = 5.0 V)
Output Coding
CMOS
Full
VI
2.8
DVCC – 0.2
V
Full
VI
0.2
0.5
V
Full
IV
4.5
DVCC – 0.3
V
Full
IV
0.35
0.5
V
Twos Complement
NOTES
1Best dynamic performance is obtained by driving ENCODE and ENCODE differentially. See Encoding the AD6640 section for more details. Performance versus ENCODE/ENCODE
power is shown in TPC 12.
2For dc-coupled applications, the ENCODE input common-mode range specifies the common-mode range the ENCODE inputs can tolerate when driven differentially by the
minimum differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value ensures
that the input voltage on either encode pin does not go below 0 V. The maximum value ensures that the input voltage on either ENCODE pin does not go below 2.0 V or above
AVCC (e.g., for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V, respectively).
3ENCODE or ENCODE may be driven alone if desired, but performance will likely be degraded. Logic compatibility specifications are provided to show that TTL or CMOS
clock sources will work. When driving only one ENCODE input, bypass the complementary input to GND with 0.01 µF.
4Digital output load is one LCX gate.
Specifications subject to change without notice.
–2–
REV. A
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