SN74LS165MR1 データシートの表示（PDF） - ON Semiconductor

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SN74LS165MR1

8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER

ON Semiconductor 

SN74LS165

DEFINITION OF TERMS:

SETUP TIME (ts) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW-to-HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW-to-HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative hold time indicates that

the correct logic level may be released prior to the clock

transition from LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the PL pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer loaded Data to the Q outputs.

AC WAVEFORMS

CP1

ts

CP2

1.3 V

Q7 OR Q7

1/fmax

tW

tPHL

tPLH

1.3 V

1.3 V

1.3 V

Figure 1.

PL

1.3 V

tPLH

Q7 OR Q7

tW

1.3 V 1.3 V

tPHL

1.3 V

1.3 V

Figure 2.

Pn

PL OR CP

1.3 V

1.3 V

ts(H)

th(H) ts(L)

th(L)

1.3 V

1.3 V

Figure 3.

PL

1.3 V

1.3 V

tW

trec

CP

1.3 V

Figure 4.

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