SN74LS156DR2 データシートの表示（PDF） - ON Semiconductor
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SN74LS156DR2 Datasheet PDF : 8 Pages
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Ea Ea
1
2
SN74LS156
LOGIC DIAGRAM
A0 A1
13
3
Eb Eb
14
15
7
6
5
4
9
10
11
12
O0a O1a O2a O3a O0b O1b O2b O3b
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with
common Address inputs and separate gated Enable inputs.
When enabled, each decoder section accepts the binary
weighted Address inputs (A0, A1) and provides four
mutually exclusive active LOW outputs (O0–O3). If the
Enable requirements of each decoder are not met, all outputs
of that decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (Ea•Ea). In demultiplexing
applications, Decoder “a” can accept either true or
complemented data by using the Ea or Ea inputs respectively.
The enable gate for Decoder “b” requires two active LOW
inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8
Decoder/Demultiplexer by tying Ea to Eb and relabeling the
common connection as (A2). The other Eb and Ea are
connected together to form the common enable.
The LS156 can be used to generate all four minterms of
two variables. These four minterms are useful in some
applications replacing multiple gate functions as shown in
Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅
(E + A0 + A1)
where E = Ea + Ea; E = Eb + Eb
E
E
A0
A1
O0
A0
A1
O0
E
E
A0
O1 A0
O1
A1
A1
E
E
A0
O2 A0
O2
A1
A1
E
E
A0
O3 A0
O3
A1
A1
Figure a
TRUTH TABLE
ADDRESS ENABLE “a”
OUTPUT “a”
ENABLE “b”
OUTPUT “b”
A0 A1 Ea Ea O0 O1 O2 O3 Eb Eb O0 O1 O2 O3
X
X
L
X
H
H
H
H
H
X
H
H
H
H
X
X
X
H
H
H
H
H
X
H
H
H
H
H
L
L
H
L
L
H
H
H
L
L
L
H
H
H
H
L
H
L
H
L
H
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
L
L
H
H
L
H
H
H
H
L
H
H
H
L
L
L
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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