SN74LS298ML2 データシートの表示（PDF） - ON Semiconductor

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SN74LS298ML2

Quad 2-Input Multiplexer with Storage

ON Semiconductor 

SN74LS298

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min Typ Max Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65 – 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

2.7

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOL

Output LOW Voltage

0.25 0.4

0.35 0.5

V

IOL = 4.0 mA

V

IOL = 8.0 mA

VCC = VCC MIN,

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

20

µA VCC = MAX, VIN = 2.7 V

0.1

mA VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

– 0.4 mA VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

– 20

– 100 mA VCC = MAX

ICC

Power Supply Current

21

mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max Unit

tPLH

Propagation Delay,

tPHL

Clock to Output

18

27

ns

21

32

ns

Test Conditions

VCC = 5.0 V,

CL = 15 pF

AC SET-UP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max Unit

tW

Clock Pulse Width

20

ns

ts

Data Setup Time

15

ns

ts

Select Setup Time

25

ns

th

Data Hold Time

5.0

ns

th

Select Hold Time

0

Test Conditions

VCC = 5.0 V

DEFINITIONS OF TERMS

SETUP TIME (ts) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW to HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW to HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW to HIGH and still be recognized.

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