LIS1R02 (L6671)
AD(3:0) = 1100 IIR_B2
This register contain the B2 coefficient used in the embedded IIR register.
AD(3:0) = 1101 IIR_SIGN_BIT
This register contain the sign bit of the coefficients used in the embedded IIR register.
AD(3:0) = 1110 DSC_Reg
This register contain the threshold value used to trigger the decimation when the Delayed Synchronous Con-
version mode is enabled.
AD(3:0) = 1111 MISC_Reg
This is the miscellaneous register.
Note: default value after Power On Reset is 0010 0000
1xxx 0x0x Force a SW reset.
x1xx xx0x Enters PLL test mode.
Bit 2-5 Define the internal oscillator division factor.
xxxx xx01 Switch to Registers Bank 1.
2.2 Registers Bank 1
AD(3:0) = 0100 CTRL_Reg1
This is the second control register.
AD(3:0) = 0101 CTRL_Reg2
This is the second control register.
AD(3:0) = 0110 FLASH_REG1
This register is used to program the embedded memory.
AD(3:0) = 0111 FLASH_REG1
This register is used to program the embedded memory.
AD(3:0) = 1000 GAIN_Low
These are the 8 LSB of gain for the adjustment unit.
AD(3:0) = 1001 GAIN_High
These are the 8 MSB of gain for the adjustment unit.
AD(3:0) = 1010 OFFSET_Low
These are the 8 LSB of offset for the adjustment unit.
AD(3:0) = 1011 OFFSET_High
These are the 8 MSB of offset for the adjustment unit.
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