LC83010N データシートの表示（PDF） - SANYO -> Panasonic
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LC83010N Datasheet PDF : 18 Pages
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Parameter
Serial clock cycle
Serial clock pulse width
Data set up time
Data hold time
Data set up time
Data hold time
LC83010N, 83010NE
Symbol
Conditions
tSCYC
tSCW
tSS
Applies to the microcomputer interface.
See figure 5.
(Applies to the SICK, SOCK and SI pins.)
tSH
Ratings
min
typ
max
650
325
75
75
tDS
Applies to the data input from external
41
DRAM. See figure 6.
tDH
(Timings between RAS, CAS and D0 to D7)
0
Unit Note
ns
ns
ns
ns
ns
8
ns
8
Electrical Characteristics at Ta = –30 to +70˚C, VDD = 4.75V to 5.25 V, VSS = 0V, unless otherwise noted
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit Note
Input low-level current
Input high-level current
Output high-level voltage
Output low-level voltage
Input leakage current
Output-off leakage current
Input/output capacitance
IIL1
IIL2
IIH
VOH1
VOH2
VOL1
VOL2
IOFF
RES, INT, VIN=VSS
P0 to P5, VIN=VSS
SELC, Input pin with pull-down resistor
IOH=– 0.4mA
IOH=– 50µA
IOH=2mA
IOH=10mA
VIN=VSS to VDD
VO=VSS, VDD
– 250
–1
4.0
VDD– 1.2
– 10
– 40
µA
mA
250 µA
V
1
V 2, 3
0.4 V
1
1.5 V 2, 3
+10 µA
+40 µA
10 pF
Output data hold time
Output data delay
tOH
Applies to audio data output.
See figure 7.
tOD
20
ns
100 ns
Output data delay
tSD
Applies to serial data output.
See figure 8.
100 ns
RAS H pulse width
RAS L pulse width
CAS H pulse width
CAS L pulse width
RAS address set up time
RAS address hold time
CAS address set up time
CAS address hold time
DWRT pulse width
CAS-before-WRITE set up time
Data set up time
Data hold time
Crystal oscillation
tRP
tRAS
tCP
tCAS
tRS
tRH
tCS
tCH
tW
tWC
tSD
tHD
C1, C2
Data output timing for external DRAM.
See figure 9.
(Note)
DRAM which has RAS access time below
120ns should be used.
OSC1, OSC2, See figure 2.
95
150
80
101
0
20
0
40
50
0
0
50
20
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
ns
8
pF
Current drain
IDD
VDD1, 2, 18.62MHz external clock
50
100 mA
(Note 1) TTL level output pins: ASO, AOBCK, AOWCK, LRCKO, BCK2, AOTDF1, AOTDF2, DFBCK, DFWCK, D0 to
D7, A0 to A8, FS384O, RAS, CAS, DREAD, DWRT and FS64O/T5
(Note 2) CMOS medium current outputs: SO, SOAK, and SIAK
(Note 3) Pu MOS medium current outputs: P0 to P5
(Note 4) TTL level outputs (first group): ASO, AOBCK, AOWCK, LRCKO, A0 to A8, D0 to D7, FS384O and BCK2
(Note 5) TTL level outputs (second group): AOTDF1, AOTDF2, DFWCK, RAS, CAS, DREAD, DWRT, and DFBCK
(Note 6) L level Schmitt inputs pin: BCK1, BCK2, ASI1, ASI2, LRCKI, and D0 to D7
(Note 7) Schmitt input pins: RES, INT, SOCK, SI, SICK, SORQ, SIRQ, and SRDY
(Note 8) The maximum load capacitance of RAS, CAS, DREAD, DWRT, D0 to D7 and A0 to A8 is 50pF.
No.3945–7/18
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