SP782 データシートの表示（PDF） - Signal Processing Technologies

部品番号

コンポーネント説明

メーカー

SP782

Programmable Charge Pump

Signal Processing Technologies 

VCC = +5V

+

C1 –

+

C2 –

–10V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 4. Charge Pump Phase 2 for ±10V.

VCC = +5V

+

C1 –

–5V

+5V

+

C2 –

–5V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 6. Charge Pump Phase 3.

The oscillator frequency or clock rate for

the charge pump is designed for low power

operation. The oscillator changes from a high

frequency mode (400kHz) to a low frequency

mode (20kHz) when the SD pin goes to a logic

"1". The lower frequency allows the SP782/

SP784 to conserve power when the outputs are

not being used.

EFFICIENCY INFORMATION

A charge pump theoretically produces a doubled

voltage at 100% efficiency. However in the real

world, there is a small voltage drop on the output

which reduces the output efficiency. The SP782

and SP784 can usually run 99.9% efficient with-

out driving a load. While driving a 1kΩ load, the

SP782 and SP784 remain at least 90% efficient.

Total Output Voltage Efficiency =

[(VOUT+) / (2*VCC)] + [(VOUT–) / (–2*VCC)] ;

VOUT+ = 2*VCC + VDROP+

VOUT– = –2*VCC + VDROP–

VDROP– = (I–)*(ROUT–)

VDROP+ = (I+)*(ROUT+)

Power Loss = IOUT*(VDROP)

The efficiency changes as the external charge

pump capacitors are varied. Larger capacitor

values will strengthen the output and reduce

output ripple usually found in all charge pumps.

Although smaller capacitors will cost less and

VCC = +5V

+

C1 –

+

C2 –

–5V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 5. Charge Pump Phase 2 for ±5V.

VCC = +5V

+

C1 –

+10V

+

C2 –

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 7. Charge Pump Phase 4.

save board space, lower values will reduce the

output drive capability.

The output voltage ripple is also affected by the

capacitors, specifically C3 and C4. Larger val-

ues will reduce the output ripple for a given load

of current. The current drawn from either output

is supplied by just the storage capacitor, C3 or

C4, during one half cycle of the internal oscilla-

tor. Note that the output current from the postive

charge pump is the load current plus the current

taken by the negative charge pump. Thus the

formula representation for the output ripple

voltage is:

VRIPPLE+ = {1 / (fOSC) * 1 / C3} * 0.5 * IOUT+

VRIPPLE– = {1 / (fOSC) * 1 / C3} * 0.5 * IOUT–

To minimize the output ripple, the C3 and C4

storage capacitors can be increased to over 10µF

whereas the pump capacitors can range from

1µF to 5µF.

Multiple SP782/784 charge pumps can be

connected in parallel. However, the output

resistance on both pump outputs will be

reduced. The effective output resistance is the

output resistance of one pump divided by the

number of charge pumps connected. It is

important to keep the C1 and C2 capacitors

separate for each charge pump. The storage

capacitors, C3 and C4, can be shared.

SP782/SP784 DS/08

SP782/784 Programmable Charge Pump

10

© Copyright 2000 Sipex Corporation

Share Link: