SP791 データシートの表示（PDF） - Signal Processing Technologies

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SP791

Low Power Microprocessor Supervisory with Battery Switch-Over

Signal Processing Technologies 

15

RESET

Corporation

TO µP RESET

10k

WDI

WDPO

WDO

1.6sec

100ns MIN

70ns

Figure 4. Adding an external pull-down resistor ensures

RESET is valid with VCC down to GND.

+5V

3

1

Vcc

VBATT

VOUT

2

3.6V

Corporation

15

RESET

WDI 11

LOWLINE 10

*1µF

+5V

9

MR

WDPO 16

WDO 14

GND

4

Figure 5. WDI, WDO and WDPO Timing

Diagram (VCC mode).

0.1µF

1/6 74HC04

3

14

5

CLOCK

D

SET

Vcc

CD4013

RESET

Q

Vss Q

2

1

6

47

µP POWER

µP

RESET

I/O

NMI

INTERRUPT

TWO

CONSECUTIVE

WATCHDOG

FAULT

INDICATIONS

REACTIVATE

4.7kΩ

∗ SETS Q HIGH ON POWER-UP

Figure 6. Two consecutive watchdog faults latch the system in reset.

MR low for a minimum of 25µs resets all the

internal counters, sets the Watchdog Output

(WDO) and Watchdog-Pulse Output (WDPO)

high, and sets the Set Watchdog-Timeout (SWT)

input to VOUT if it is not already connected to

VOUT (for Internal timeouts). It also, disables

the Chip-Enable Output (CE OUT) forcing it to

a high state. The RESET output remains at a

logic low as long as MR is held low, and the

reset-timeout period begins after MR returns

high, Figure 2.

Use this input as either a digital-logic input or a

second low-line comparator. Normal TTL/

CMOS levels can be wire-OR connected via

pull-down diodes, Figure 3, and open-drain/col-

lector outputs can be wire-ORed directly.

RESET OUTPUT

The SP791's RESET output ensures that the µP

powers up in a known state, and prevents code-

execution errors during power-down or brown-

out conditions.

The RESET output is active low, and typically

sinks 3.2mA at 0.1V saturation voltage in its

active state. When deasserted, RESET sources

1.6mA at VOUT – 0.5V. When no backup bat-

tery is used, RESET output is valid down to VCC

= 1V, and an external 10kΩ pull-down resistor

on RESET ensures that RESET will be valid

with VCC down to GND as shown on Figure 4.

As VCC goes below 1V, the gate drive to the

RESET output switch reduces accordingly,

increasing the r (ON) and the saturation volt-

DS

age. The 10kΩ pull-down resistor ensures the

parallel combination of switch and external

resistor is 10kΩ and the output saturation volt-

age is below 0.4V, while sinking 40µA. When

using a 10kΩ external pull-down resistor, the

high state for the RESET output with Vcc =

4.75V is 4.5V typical. For battery voltages

greater than or equal to 2V, RESET remains

valid for VCC between 0V and 5.5V. RESET will

be asserted during the following conditions:

1) VCC < 4.65V (typ)

2) MR < 1.25V (typ)

3) RESET = logic "0" ; for 200 ms (typ) after

Vcc rises above 4.65V or after MR has exceeded

1.25V.

The SP791 battery-switchover comparator does

not affect RESET assertion.

SP791DS/08

SP791 Low Power Microprocessor Supervisory with Battery Switch-Over

9

© Copyright 2000 Sipex Corporation

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