5962-90618 データシートの表示（PDF） - Zarlink Semiconductor Inc
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5962-90618 Datasheet PDF : 7 Pages
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CLOCK INPUT
PE INPUT
OUTPUT
tr
6
ts
5
5
Fig. 4 Timing diagram
j1
j 0.5
j2
SP8647
TRUTH TABLE FOR
CONTROL INPUTS
PE1 PE2 Division ratio
L
L
11
H
L
10
L
H
10
H
H
10
j 0.2
j5
0
0.2
0.5
2j 0.2
1
2
5
50
100
2j 5
150
250 200
2j 2
2j 0.5
2j 1
Fig. 5 Typical input impedance. Test conditions: Supply Voltage = 5V,
Ambient Temperature = 25°C. Frequencies in MHz, impedances normalised to 50Ω.
OPERATING NOTES
1. The clock and control inputs are ECLIII compatible. There
is an internal pulldown resistor to VEE of 4·3kΩ on each input
and therefore any unused input can be left open circuit. If it
is desirable to capacitively couple the signal source to the
clock then an external bias is required as shown in Fig. 6.
The external bias voltage should be 21·3V at 25°C.
2. The outputs are compatible with ECLII but can be interfaced
to ECL10K as shown in Fig.8.
3. The circuit will operate down to DC but slew rate must be
better than 100V/µs.
4. Input impedance is a function of frequency. See Fig. 5.
5. The TTL/CMOS output is a free collector, with an output
rise/fall time which is a function of load resistance and load
capacitance. The load capacitance should therefore be kept
to a minimum and the load resistance should not be too
small otherwise VOL will be too great. For example, TTL
output current = 8mA, VOL = 0·5V. For CMOS outputs, the
value of load resistor should be the maximum consistent
with satisfactory rise times.
6. All components should be suitable for the frequency in use.
3
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