SP8605KN データシートの表示（PDF） - Signal Processing Technologies

部品番号

コンポーネント説明

メーカー

SP8605KN

12-Bit Sampling A/D Converters

Signal Processing Technologies 

To avoid introducing distortion, the source resistance

must be very low, or constant with signal level. The

output impedance provided by most op amps is ideal.

Pins 26 Digital Supply Voltage (VSD) and 27 Analog

SupplyVoltage (V )arebroughtouttoseparatepins

SA

to maximize accuracy on the chip. They should be

connected together as close as possible to the unit. Pin

27 may be slightly more sensitive than pin 26 to supply

variations, but to maintain maximum system accu-

racy, both should be well–isolated from digital sup-

plies with wide load variations.

To limit the effects of digital switching elsewhere in a

system on the analog performance of the system, it

often makes sense to run a separate +5V supply

conductor from the supply regulator to any analog

components requiring +5V, including the SP86XX

Series. If the SP86XX Series traces cannot be

separated back to the power supply terminals, and

therefore share the same trace as the logic supply

currents, then a 10 Ohm isolating resistor should be

used between the board supply and pin 24 (VDA) and

its bypass capacitors to keep VDA glitch–free. The VS

pins (26 and 27) should be connected together and

bypassed with a parallel combination of a 6.8µF

Tantalum capacitor and a 0.1µF ceramic capacitor

located close to the converter to obtain noise-free

operation. (See Figure 1). Noise on the power supply

lines can degrade converter performance, especially

noise and spikes from a switching power supply.

Appropriate supplies or filters must be used.

The GND pins (5 and 16) are also separated internally,

and should be directly connected to a ground plane

under the converter. A ground plane is usually the best

solution for preserving dynamic performance and

reducing noise coupling into sensitive converter cir-

cuits. Where any compromises must be made, the

common return of the analog input signal should be

referenced to pin 5, AGND, on the SP86XX Series,

which prevents any voltage drops that might occur in

the power supply common returns from appearing in

series with the input signal.

Coupling between analog input and digital lines should

be minimized by careful layout. For instance, if the

lines must cross, they should do so at right angles.

Parallel analog and digital lines should be separated

from each other by a pattern connected to common.

If external full scale and offset potentiometers are

used, the potentiometers and related resistors should

be located as close to the SP86XX Series as possible.

“Hot Socket” Precaution

Two separate +5V VS pins, 26 and 27, are used to

minimize noise caused by digital transients. If one pin

is powered and the other is not, the SP86XX Series

may draw excessive current. In normal operation, this

is not a problem because both pins will be soldered

together. However, during evaluation, incoming in-

spection, repair, etc., where the potential of a “Hot

Socket” exists, care should be taken to apply power to

R/C

tB

BUSY

t DBC

tC

Converter Acquisition

Mode

Conversion

tAP

Hold Time

Acquisition

Conversion

SYMBOL/PARAMETER

tDBC BUSY delay from R/C

tB BUSY Low

MIN.

tAP Aperture Delay

∆tAP Aperture Jitter

tC Conversion Time

TYP.

80

2.5

4.5

9.5

13

150

2.47

4.47

9.47

MAX.

150

2.7

4.7

9.7

2.70

4.70

9.70

UNITS

ns

µs

µs

µs

ns

ps, rms

µs

µs

µs

Figure 4. Acquisition and Conversion Timing

86

SP8603

SP8605

SP8610

SP8603

SP8605

SP8610

Share Link: