SP8605KN データシートの表示（PDF） - Signal Processing Technologies

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SP8605KN

12-Bit Sampling A/D Converters

Signal Processing Technologies 

R/C

tW

BUSY

Converter

Mode

Data

BUS

tB

tDBC

Acquire

Data Valid

tAP

t DBE

Convert

tC

tHDR and tHL

Hi-Z State

Acquire

tA

t DB

Data Valid

Convert

Hi-Z State

Figure 5. Convert Mode Timing — R/C Pulse LOW, Outputs Enabled After Conversion

the SP86XX Series only after it has been socketed.

Minimizing “Glitches”

Coupling of external transients into an analog-to-

digital converter can cause errors which are difficult to

debug. In addition to the discussions earlier on layout

considerations for supplies, bypassing and grounding,

there are several other useful steps that can be taken to

get the best analog performance out of a system using

the SP86XX Series. These potential system problem

sources are particularly important to consider when

developing a new system, and looking for the causes

of errors in breadboards.

First, care should be taken to avoid glitches during

critical times in the sampling and conversion process.

Since the SP86XX Series has an internal sample/hold

function, the signal that puts it into the hold state (R/C

going LOW) is critical, as it would be on any sample/

hold amplifier. The R/C falling edge should have a 5

to 10ns transition time, low jitter, and have minimal

ringing, especially during the 20ns after it falls.

Although not normally required, it is also good prac-

tice to avoid glitches from coupling to the SP86XX

Series while bit decisions are being made. Since the

above discussion calls for a fast, clean rise and fall on

R/C

tW

BUSY

Converter

Mode

Data

BUS

tB

tDBC

Acquire

tDD

Hi-Z State

Data

Valid

tAP

t DBE

Convert

tC

tHDR and tHL

Hi-Z State

Acquire

tA

tAP

Convert

Data

Valid

Hi-Z State

Figure 6. Read Mode Timing — R/C Pulse HIGH, Outputs Enabled Only When R/C is High

87

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