BSP3505D データシートの表示（PDF） - Micronas

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BSP3505D

Baseband sound processor

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PRELIMINARY DATA SHEET

BSP 3505D

3. I2C Bus Interface: Device and Subaddresses

As a slave receiver, the BSP 3505D can be controlled via

I2C bus. Access to internal memory locations is

achieved by subaddressing. The DSP processor part

has its own subaddressing register bank.

In order to allow for more BSP or MSP ICs to be con-

nected to the control bus, an ADR_SEL pin has been im-

plemented. With ADR_SEL pulled to high, low, or left

open, the BSP 3505D responds to changed device ad-

dresses. Thus, three identical devices can be selected.

By means of the RESET bit in the CONTROL register,

all devices with the same device address are reset.

The IC is selected by asserting a special device address

in the address part of an I2C transmission. A device ad-

dress pair is defined as a write address (80, 84, or 88hex)

and a read address (81, 85, or 89hex). Writing is done by

sending the device write address first, followed by the

subaddress byte, two address bytes, and two data by-

tes. Reading is done by sending the device write ad-

dress, followed by the subaddress byte and two address

bytes. Without sending a stop condition, reading of the

addressed data is completed by sending the device read

address (81, 85, or 89hex) and reading two bytes of data.

Refer to Fig. 3–1: I2C Bus Protocol and section 3.2. Pro-

posal for BSP 3505D I2C Telegrams.

Due to the internal architecture of the BSP 3505D the IC

cannot react immediately to an I2C request. The typical

response time is about 0.3 ms for the DSP processor

part. If the receiver (BSP) can’t receive another com-

plete byte of data until it has performed some other func-

tion; for example, servicing an internal interrupt, it can

hold the clock line I2C_CL LOW to force the transmitter

into a wait state. The positions within a transmission

where this may happen are indicated by ’Wait’ in section

3.1. The maximum Wait-period of the BSP during normal

operation mode is less than 1 ms.

I2C-Bus conditions caused by BSP hardware problems:

In case of any internal error, the BSPs wait-period is ex-

tended to 1.8 ms. Afterwards, the BSP does not ac-

knowledge (NAK) the device address. The data line will

be left HIGH by the BSP and the clock line will be re-

leased. The master can then generate a STOP condition

to abort the transfer.

By means of NAK, the master is able to recognize the er-

ror state and to reset the IC via I2C-Bus. While transmit-

ting the reset protocol (s. 5.2.4.) to ‘CONTROL’, the

master must ignore the not acknowledge bits (NAK) of

the BSP.

A general timing diagram of the I2C Bus is shown in

Fig. 3–2.

Table 3–1: I2C Bus Device Addresses

ADR_SEL

Mode

BSP device address

Write

80hex

Low

Read

81hex

Write

84hex

High

Read

85hex

Left Open

Write

Read

88hex

89hex

Table 3–2: I2C Bus Subaddresses

Name

CONTROL

TEST

WR_DSP

RD_DSP

Binary Value

0000 0000

0000 0001

0001 0010

0001 0011

Hex Value

00

01

12

13

Mode

Write

Write

Write

Write

Function

software reset

only for internal use

write address DSP

read address DSP

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