BSP3505D データシートの表示（PDF） - Micronas

部品番号

コンポーネント説明

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BSP3505D

Baseband sound processor

Micronas 

BSP 3505D

Table 3–3: Control Register (Subaddress: 00hex)

Name

Subaddress

MSB

14

CONTROL

00hex

1 : RESET

0

0 : normal

PRELIMINARY DATA SHEET

13..1

0

LSB

0

3.1. Protocol Description

Write to DSP

S

write

Wait ACK sub-addr ACK addr-byte ACK addr-byte low ACK data-byte high ACK data-byte low ACK P

device

high

address

Read from DSP

S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S

device

high

low

address

read

device

address

ÇÇÇ ÇÇÇ Wait ACK data-byte ACK data-byte NAK P

ÇÇÇÇÇÇ ÇÇÇÇÇÇ high

low

Write to Control or Test Registers

S

write

Wait ACK

device

address

sub-addr

ACK

data-byte high

ACK

data-byte low

ACK P

Note: S =

P=

ACK =

NAK =

Wait =

I2C-Bus Start Condition from master

I2C-Bus Stop Condition from master

Acknowledge-Bit: LOW on I2C_DA from slave (= BSP, gray)

or master (= CCU, hatched)

Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate ‘End of Read’

or from BSP indicating internal error state

I2C-Clock line held low by the slave (= BSP) while interrupt is serviced (<1.8 ms)

I2C_DA

S

I2C_CL

Fig. 3–1: I2C bus protocol

(Data: MSB first)

1

0

P

(MSB first; data must be stable while clock is high)

8

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