MC14511B データシートの表示（PDF） - Motorola => Freescale
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MC14511B Datasheet PDF : 9 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎACÎÎÎÎTERÎÎÎÎISTÎÎÎÎICSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ) ÎÎÎÎÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic
Symbol
Vdc
Min
Typ
Max
Unit
Output Rise Time
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH = (0.20 ns/pF) CL + 15 ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
Data Propagation Delay Time
tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tTLH
ns
5.0
—
40
80
10
—
30
60
15
—
25
50
tTHL
ns
5.0
—
125
250
10
—
75
150
15
—
65
130
tPLH
ns
5.0
—
640
1280
10
—
250
500
15
—
175
350
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL
5.0
—
720
1440
10
—
290
580
15
—
200
400
Blank Propagation Delay Time
tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPLH
ns
5.0
—
600
750
I0
—
200
300
15
—
150
220
tPHL
5.0
—
485
970
10
—
200
400
15
—
160
320
Lamp Test Propagation Delay Time
tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns
tPLH
ns
5.0
—
313
625
10
—
125
250
15
—
90
180
tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
—
313
625
10
—
125
250
15
—
90
180
Setup Time
tsu
5.0
100
—
—
ns
10
40
—
—
15
30
—
—
Hold Time
th
5.0
60
—
—
ns
10
40
—
—
15
30
—
—
Latch Enable Pulse Width
tWL
5.0
520
260
—
ns
10
220
110
—
15
130
65
—
* The formulas given are for the typical characteristics only.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range VSS ≤ (Vin or
Vout) ≤ VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
MOTOROLA CMOS LOGIC DATA
MC14511B
363
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