ML4828CP データシートの表示（PDF） - Micro Linear Corporation

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ML4828CP

BiCMOS Phase Modulation/Soft Switching Controller

Micro Linear Corporation 

ML4828

ISWITCH

V+

7 SS

CSS

R1

RSENSE

ILIM

20

C1

+

1V

–

V+

I1

TERMINATE

PWM CYCLE

S

Q

RRST

CRST

IRST

12 RST

R

CLOCK

+

2.5V

1.25V

–

INHIBIT

OUTPUT

UNDER-VOLTAGE

LOCKOUT

Figure 5. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.

SOFT START TIME CONSTANT

During start up, the output voltage is much lower than the

steady state value. Without soft start circuitry, the error

amplifier output (EAO) would swing all the way to the

upper limit and the phase modulator would issue pulses

with full duty cycle, possibly causing output overshoot. To

ensure smooth start up, EAO (pin 8) is pulled low and

then gradually released through the charging of an

external soft start capacitor connected to SS (pin 7). The

soft start charging current is internally set at 25µA. Hence,

EAO will rise with a time constant of:

dv = 25µA

dt CSS

(9)

For example, with CSS = 25µF, the soft start rate of change

will be:

dv = 25µA = 1V

dt 25µF s

(10)

FAULT TIME CONSTANT AND RESTART DELAY

Figure 5 shows the internal circuitry and external

components involved in fault detection. During normal

operation, RST (pin 12) is discharged to ground through

the external resistor RRST. The ILIM comparator has a

threshold of 1V. RSENSE is selected so that the voltage

across it will be equal to the ILIM threshold at the

maximum desired ISWITCH current. When the voltage

across RSENSE exceeds 1V, the ILIM comparator trips,

terminating the present power cycle, and at the same time

activating the fault logic to turn on the 500µA current

source IRST. This current charges the reset capacitor CRST.

For proper design, RRST should be very large (in the order

of 100kΩ). This will cause nearly all of the IRST current

(approximately 500µA) to go into charging CRST at a rate of:

dv = 500µA

dt CRST

(11)

in volts per second. IRST will be turned off at the beginning

of the next clock cycle. If the current limit condition is

removed, RST will be gradually discharged to ground,

and normal operation resumes as shown in Figure 6.

1V

V(PIN 20)

2.5V

V(PIN 12)

Figure 6. ILIM and Resulting RCRST

Waveforms During Load Surge.

7

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