SST29EE010A データシートの表示（PDF） - Silicon Storage Technology
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SST29EE010A Datasheet PDF : 26 Pages
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1 Megabit Page Mode EEPROM
SST29EE010A / SST29LE010A / SST29VE010A
Write Operation Status Detection
Data Protection
The SST29EE010A/29LE010A/29VE010A provide two The SST29EE010A/29LE010A/29VE010A provide both
software means to detect the completion of a write cycle,
in order to optimize the system write cycle time. The
hardware and software features to protect nonvolatile
data from inadvertent writes.
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software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising WE# or CE# whichever
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
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occurs first, which initiates the internal write cycle.
5 ns will not initiate a write cycle.
The actual completion of the nonvolatile write is asyn-
VCC Power Up/Down Detection: The write operation is
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chronous with the system; therefore, either a Data# inhibited when VCC is less than 2.5V.
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation. This prevents inad-
vertent writes during power-up or power-down.
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prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
Software Data Protection (SDP)
The SST29EE010A/29LE010A/29VE010A provide the
JEDEC approved software data protection scheme for
all data alteration operations, i.e., Write and Chip Erase.
With this scheme, any Write operation requires the
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Data# Polling (DQ7)
When the SST29EE010A/29LE010A/29VE010A are in
the internal write cycle, any attempt to read DQ7 of the
last byte loaded during the byte-load cycle will receive
the complement of the true data. Once the write cycle is
inclusion of a series of three byte-load operations to
precede the data loading operation. The three byte-load
sequence is used to initiate the write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down.
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completed, DQ7 will show true data. The device is then
ready for the next operation. See Figure 6 for Data#
Polling timing diagram and Figure 14 for a flowchart.
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Toggle Bit (DQ6)
During the internal write cycle, any consecutive attempts
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to read DQ6 will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is
completed, the toggling will stop. The device is then
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ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 14 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
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© 1999 Silicon Storage Technology, Inc.
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303-01 2/99
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