SST29SF010 データシートの表示（PDF） - Silicon Storage Technology
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SST29SF010 Datasheet PDF : 24 Pages
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash
SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040
SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040
Preliminary Specifications
Data# Polling (DQ7)
When the SST29SFxxx and SST29VFxxx devices are in
the internal Program operation, any attempt to read DQ7
will produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. The device is then ready for the next operation. Dur-
ing internal Erase operation, any attempt to read DQ7 will
produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Pro-
gram operation. For Sector- or Chip-Erase, the Data# Poll-
ing is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 7 for Data# Polling timing diagram and
Figure 17 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-
gram and Figure 17 for a flowchart.
Data Protection
The SST29SFxxx and SST29VFxxx devices provide both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V for SST29SFxxx. The
Write operation is inhibited when VDD is less than 1.5V. for
SST29VFxxx.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29SFxxx and SST29VFxxx provide the JEDEC
approved Software Data Protection scheme for all data
alteration operation, i.e., Program and Erase. Any Program
operation requires the inclusion of a series of three byte
sequence. The three byte-load sequence is used to initiate
the Program operation, providing optimal protection from
inadvertent write operations, e.g., during the system power-
up or power-down. Any Erase operation requires the inclu-
sion of six byte load sequence. These devices are shipped
with the Software Data Protection permanently enabled.
See Table 4 for the specific software command codes. Dur-
ing SDP command sequence, invalid commands will abort
the device to read mode, within TRC.
Product Identification
The Product Identification mode identifies the devices as
SST29SF512, SST29SF010, SST29SF020, SST29SF040
and SST29VF512, SST29VF010, SST29VF020,
SST29VF040 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry and Read
timing diagram and Figure 18 for the Software ID Entry
command sequence flowchart.
TABLE 1: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST29SF512
SST29VF512
SST29SF010
SST29VF010
SST29SF020
SST29VF020
SST29SF040
SST29VF040
Address
0000H
0001H
0001H
0001H
0001H
0001H
0001H
0001H
0001H
Data
BFH
20H
21H
22H
23H
24H
25H
13H
14H
T1.1 505
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form and Figure 18 for a flowchart.
©2001 Silicon Storage Technology, Inc.
3
S71160-05-000 5/01 505
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