SST32HF802-70-4C-L3K データシートの表示（PDF） - Silicon Storage Technology

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SST32HF802-70-4C-L3K

Multi-Purpose Flash (MPF) + SRAM ComboMemory

Silicon Storage Technology 

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

Data Sheet

The SST32HF202/402/802 devices are suited for applica-

tions that use both flash memory and SRAM memory to

store code or data. For systems requiring low power and

small form factor, the SST32HF202/402/802 devices signif-

icantly improve performance and reliability, while lowering

power consumption, when compared with multiple chip

solutions. The SST32HF202/402/802 inherently use less

energy during erase and program than alternative flash

technologies. The total energy consumed is a function of

the applied voltage, current, and time of application. Since

for any given voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternative flash technologies.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose

Erase and Program times increase with accumulated

Erase/Program cycles.

Device Operation

The ComboMemory uses BES# and BEF# to control oper-

ation of either the SRAM or the flash memory bank. When

BES# is low, the SRAM Bank is activated for Read and

Write operation. When BEF# is low the flash bank is acti-

vated for Read, Program or Erase operation. BES# and

BEF# cannot be at low level at the same time. If BES# and

BEF# are both asserted to low level bus contention will

result and the device may suffer permanent damage.

All address, data, and control lines are shared by SRAM

Bank and flash bank which minimizes power consumption

and loading. The device goes into standby when both bank

enables are high.

SRAM Operation

With BES# low and BEF# high, the SST32HF202/402/802

operate as 128K x16 CMOS SRAM, with fully static opera-

tion requiring no external clocks or timing strobes. The

SST32HF202/402/802 SRAM is mapped into the first 128

KWord address space. When BES# and BEF# are high,

both memory banks are deselected and the device enters

standby mode. Read and Write cycle times are equal. The

control signals UBS# and LBS# provide access to the

upper data byte and lower data byte. See Table 3 for SRAM

Read and Write data byte control modes of operation.

SRAM Read

The SRAM Read operation of the SST32HF202/402/802 is

controlled by OE# and BES#, both have to be low with

WE# high for the system to obtain data from the outputs.

BES# is used for SRAM bank selection. OE# is the output

control and is used to gate data from the output pins. The

data bus is in high impedance state when OE# is high. See

Figure 3 for the Read cycle timing diagram.

SRAM Write

The SRAM Write operation of the SST32HF202/402/802 is

controlled by WE# and BES#, both have to be low for the

system to write to the SRAM. During the Word-Write oper-

ation, the addresses and data are referenced to the rising

edge of either BES# or WE#, whichever occurs first. The

write time is measured from the last falling edge to the first

rising edge of BES# or WE#. See Figures 4 and 5 for the

Write cycle timing diagrams.

Flash Operation

With BEF# active, the SST32HF202 operates as 128K x16

flash memory, the SST32HF402 operates as 256K x16

flash memory, and the SST32HF802 operates as 512K

x16 flash memory. The flash memory bank is read using

the common address lines, data lines, WE# and OE#.

Erase and Program operations are initiated with the

JEDEC standard SDP command sequences. Address and

data are latched during the SDP commands and during the

internally-timed Erase and Program operations.

Flash Read

The Read operation of the SST32HF202/402/802 devices

is controlled by BEF# and OE#. Both have to be low, with

WE# high, for the system to obtain data from the outputs.

BEF# is used for flash memory bank selection. When

BEF# and BES# are high, both banks are deselected and

only standby power is consumed. OE# is the output con-

trol and is used to gate data from the output pins. The data

bus is in high impedance state when OE# is high. Refer to

Figure 6 for further details.

©2005 Silicon Storage Technology, Inc.

2

S71209-06-000

5/05

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