SST32HF802-70-4E-LBKE データシートの表示（PDF） - Silicon Storage Technology

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SST32HF802-70-4E-LBKE

Multi-Purpose Flash (MPF) + SRAM ComboMemory

Silicon Storage Technology 

Multi-Purpose Flash (MPF) + SRAM ComboMemory

SST32HF202 / SST32HF402 / SST32HF802

Data Sheet

Flash Data# Polling (DQ7)

When the SST32HF202/402/802 flash memory banks are

in the internal Program operation, any attempt to read DQ7

will produce the complement of the true data. Once the

Program operation is completed, DQ7 will produce true

data. Note that even though DQ7 may have valid data

immediately following the completion of an internal Write

operation, the remaining data outputs may still be invalid:

valid data on the entire data bus will appear in subsequent

successive Read cycles, after an interval of 1 µs. During

internal Erase operation, any attempt to read DQ7 will pro-

duce a ‘0’. Once the internal Erase operation is completed,

DQ7 will produce a ‘1’. The Data# Polling is valid after the

rising edge of the fourth WE# (or BEF#) pulse for Program

operation. For Sector- or Block-Erase, the Data# Polling is

valid after the rising edge of the sixth WE# (or BEF#) pulse.

See Figure 9 for Data# Polling timing diagram and Figure

19 for a flowchart.

Flash Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating ‘1’s

and ‘0’s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the toggling will

stop. The flash memory bank is then ready for the next

operation. The Toggle Bit is valid after the rising edge of the

fourth WE# (or BEF#) pulse for Program operation. For

Sector- or Bank-Erase, the Toggle Bit is valid after the rising

edge of the sixth WE# (or BEF#) pulse. See Figure 10 for

Toggle Bit timing diagram and Figure 19 for a flowchart.

Flash Memory Data Protection

The SST32HF202/402/802 flash memory bank provides

both hardware and software features to protect nonvolatile

data from inadvertent writes.

Flash Software Data Protection (SDP)

The SST32HF202/402/802 provide the JEDEC approved

software data protection scheme for all flash memory bank

data alteration operations, i.e., Program and Erase. Any

Program operation requires the inclusion of a series of

three-byte sequence. The three-byte load sequence is

used to initiate the Program operation, providing optimal

protection from inadvertent Write operations, e.g., during

the system power-up or power-down. Any Erase operation

requires the inclusion of six-byte load sequence. The

SST32HF202/402/802 devices are shipped with the soft-

ware data protection permanently enabled. See Table 4 for

the specific software command codes. During SDP com-

mand sequence, invalid SDP commands will abort the

device to the Read mode, within Read cycle time (TRC).

Concurrent Read and Write Operations

The SST32HF202/402/802 provide the unique benefit of

being able to read from or write to SRAM, while simulta-

neously erasing or programming the Flash. This allows

data alteration code to be executed from SRAM, while alter-

ing the data in Flash. The following table lists all valid states.

CONCURRENT READ/WRITE STATE TABLE

Flash

Program/Erase

Program/Erase

SRAM

Read

Write

The device will ignore all SDP commands when an Erase

or Program operation is in progress. Note that Product

Identification commands use SDP; therefore, these com-

mands will also be ignored while an Erase or Program

operation is in progress.

Flash Hardware Data Protection

Noise/Glitch Protection: A WE# or BEF# pulse of less than

5 ns will not initiate a Write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#

high will inhibit the Flash Write operation. This prevents

inadvertent writes during power-up or power-down.

©2005 Silicon Storage Technology, Inc.

4

S71209-06-000

5/05

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