SST36VF1601G データシートの表示（PDF） - Silicon Storage Technology
部品番号
コンポーネント説明
メーカー
SST36VF1601G Datasheet PDF : 36 Pages
| |||
Data Sheet
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high-density, surface-mount requirements, the
SST36VF1601G and SST36VF1602G devices are offered
in 48-ball TFBGA, 48-lead TSOP, and 56-ball LFBGA
packages. See Figures 6, 7, and 8 for pin assignments.
Device Operation
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
Auto Low Power Mode
These devices also have the Auto Lower Power mode
which puts them in a near-standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the typical IDD active Read current to 4 µA.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank. See Table 1 below
for more information.
TABLE 1: Concurrent Read/Write State
Bank 1
Read
Read
Write
Write
No Operation
No Operation
Bank 2
No Operation
Write
Read
No Operation
Read
Write
Note: For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
The Read operation of the SST36VF160xG is controlled
by CE# and OE#, both of which have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in a high impedance state when either CE# or
OE# is high. Refer to Figure 9, the Read cycle timing dia-
gram, for further details.
Program Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, ensure that the sector which is
being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Initiate Software Data Protection using the three-
byte load sequence.
2. Load address and data.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initi-
ated, will be completed typically within 7 µs.
See Figures 10 and 11 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 25 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
©2006 Silicon Storage Technology, Inc.
2
S71342-00-000
12/06
Share Link: 