SST39SF512 データシートの表示（PDF） - Silicon Storage Technology

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SST39SF512

512 Kbit / 1 Mbit (x8) Multi-Purpose Flash

Silicon Storage Technology 

512 Kbit / 1 Mbit Multi-Purpose Flash

SST39SF512 / SST39SF010

Data Sheet

TABLE 2: PIN DESCRIPTION

Symbol

AMS1-A0

Pin Name

Address Inputs

DQ7-DQ0 Data Input/output

CE#

OE#

WE#

VDD

VSS

NC

Chip Enable

Output Enable

Write Enable

Power Supply

Ground

No Connection

Functions

To provide memory addresses.

During Sector-Erase AMS-A12 address lines will select the sector.

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

To activate the device when CE# is low.

To gate the data output buffers.

To control the Write operations.

To provide 5.0V supply (±10%)

Unconnected pins.

1. AMS = Most significant address

AMS = A15 for SST39SF512 and A16 for SST39SF010

T2.3 394

TABLE 3: OPERATION MODES SELECTION

Mode

Read

Program

Erase

CE#

VIL

VIL

VIL

OE#

VIL

VIH

VIH

WE#

VIH

VIL

VIL

DQ

DOUT

DIN

X1

Standby

Write Inhibit

Product Identification

Software Mode

VIH X

X High Z

X

VIL

X High Z/ DOUT

X

X VIH High Z/ DOUT

VIL VIL VIH

1. X can be VIL or VIH, but no other value.

Address

AIN

AIN

Sector address,

XXH for Chip-Erase

X

X

X

See Table 4

T3.4 394

©2001 Silicon Storage Technology, Inc.

6

S71149-03-000 4/01 394

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