SST39SF020-90-4I-W データシートの表示（PDF） - Silicon Storage Technology
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SST39SF020-90-4I-W Datasheet PDF : 23 Pages
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2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
A17-A0
Address Inputs
DQ7-DQ0 Data Input/output
CE#
OE#
WE#
Vcc
Vss
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Functions
To provide memory addresses. During sector erase A17-A12 address lines
1
will select the sector.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
2
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
3
To control the write operations.
To provide 5-volt supply (± 10%)
4
Unconnected pins.
326 PGM T2.1
5
TABLE 3: OPERATION MODES SELECTION
Mode
CE# OE# WE# A9 DQ
6
Address
Read
VIL VIL
VIH
AIN
DOUT
AIN
Program
VIL VIH
VIL
AIN
DIN
AIN
7
Erase
Standby
VIL VIH
VIH X
VIL
X
X
X
X
High Z
Sector address, XXh for
chip erase
X
8
Write Inhibit
X
VIL
X
X
High Z/DOUT
X
X
X
VIH
X
High Z/DOUT
X
Product Identification
9
Hardware Mode
VIL VIL
VIH
VH
Manufacturer Code (BF) A17 - A1 = VIL, A0 = VIL
Software Mode
VIL VIL
Device Code (B6)
VIH AIN ID Code
A17 - A1 = VIL, A0 = VIH
See Table 4
10
326 PGM T3.4
11
12
13
14
15
16
© 1998 Silicon Storage Technology, Inc.
5
326-10 12/98
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