SST39VF1601-70-4I-B3K データシートの表示（PDF） - Silicon Storage Technology

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SST39VF1601-70-4I-B3K

16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus

Silicon Storage Technology 

16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus

SST39VF1601 / SST39VF3201 / SST39VF6401

SST39VF1602 / SST39VF3202 / SST39VF6402

Preliminary Specifications

ADDRESS AMS-0

TRC

TAA

CE#

TCE

OE#

TOE

WE#

DQ15-0

VIH

TOLZ

TOHZ

HIGH-Z

TCLZ

TOH

DATA VALID

TCHZ

DATA VALID

HIGH-Z

Note: AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

1223 F03.2

FIGURE 3: READ CYCLE TIMING DIAGRAM

ADDRESS AMS-0

WE#

TAS

OE#

5555

TAH

TWP

2AAA

TWPH

5555

ADDR

TDS

INTERNAL PROGRAM OPERATION STARTS

TBP

TDH

TCH

CE#

DQ15-0

XXAA

TCS

XX55

XXA0

DATA

Note:

SW0

SW1

SW2

WORD

(ADDR/DATA)

1223 F04.3

AMS = Most significant address

AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence

X can be VIL or VIH, but no other value

FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

©2003 Silicon Storage Technology, Inc.

15

S71223-03-000

11/03

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