SST39VF1601-70-4I-B3K データシートの表示（PDF） - Silicon Storage Technology
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SST39VF1601-70-4I-B3K
Silicon Storage Technology
SST39VF1601-70-4I-B3K Datasheet PDF : 32 Pages
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Preliminary Specifications
16 Mbit / 32 Mbit / 64 Mbit Multi-Purpose Flash Plus
SST39VF1601 / SST39VF3201 / SST39VF6401
SST39VF1602 / SST39VF3202 / SST39VF6402
SIX-BYTE CODE FOR BLOCK-ERASE
TBE
ADDRESS AMS-0
5555 2AAA
5555
5555
2AAA
BAX
CE#
OE#
WE#
TWP
DQ15-0
XXAA XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
FIGURE
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
BAX = Block Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
1223 F09.4
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
ADDRESS AMS-0
5555 2AAA
5555
5555
2AAA
SAX
CE#
OE#
WE#
TWP
DQ15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX30
SW5
Note:
This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 17)
SAX = Sector Address
AMS = Most significant address
AMS = A19 for SST39VF1601/1602, A20 for SST39VF3201/3202, and A21 for SST39VF6401/6402
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence
X can be VIL or VIH, but no other value
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1223 F10.4
©2003 Silicon Storage Technology, Inc.
18
S71223-03-000
11/03
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