SST49LF002A データシートの表示（PDF） - Silicon Storage Technology
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SST49LF002A Datasheet PDF : 36 Pages
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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Do not violate processor or chipset limitations on the INIT# pin.
2. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI outputs.
OPERATING RANGE
Range
Commercial
Ambient Temp
0°C to +85°C
VDD
3.0-3.6V
AC CONDITIONS OF TEST1
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 24 and 25
1. FWH interface signals use PCI load test conditions
TABLE 11: DC OPERATING CHARACTERISTICS (ALL INTERFACE)
Limits
Symbol Parameter
IDD
Power Supply Current
Min
Max
Units
ISB
IRY1
II
ILI
ILO
VIHI2
VILI2
VIL
VIH
VOL
VOH
Read
12
mA
Write
24
mA
Standby VDD Current
(FWH Interface)
100
µA
Ready Mode VDD Current
(FWH Interface)
10
mA
Input Current for IC,
ID [3:0] pins
200
µA
Input Leakage Current
1
µA
Output Leakage Current
1
µA
INIT# Input High Voltage
INIT# Input Low Voltage
1.0
VDD+0.5
V
-0.5
0.4
V
Input Low Voltage
-0.5
0.3 VDD
V
Input High Voltage
Output Low Voltage
0.5 VDD VDD+0.5
V
0.1 VDD
V
Output High Voltage
0.9 VDD
V
1. The device is in Ready Mode when no activity is on the FWH bus.
2. Do not violate processor or chipset specification regarding INIT# voltage.
Test Conditions
Address input=VIL/VIH, at F=1/TRC Min,
VDD=VDD Max (PP Mode)
OE#=VIH, WE#=VIH
OE#=VIH, WE#=VIL, VDD=VDD Max (PP Mode)
FWH4=0.9VDD, f=33 MHz VDD=VDD Max, All
other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
FWH4=VIL, f=33 MHz VDD=VDD Max All other
inputs ≥ 0.9 VDD or ≤ 0.1 VDD
VIN=GND to VDD, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Max
VDD=VDD Min
VDD=VDD Min
VDD=VDD Max
IOL=1500µA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
T11.8 504
©2001 Silicon Storage Technology, Inc.
19
S71161-06-000 9/01 504
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