SST49LF002A データシートの表示（PDF） - Silicon Storage Technology
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SST49LF002A Datasheet PDF : 36 Pages
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2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
TPU-READ1
TPU-WRITE1
Parameter
Power-up to Read Operation
Power-up to Write Operation
Minimum
100
100
Units
µs
µs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
T12.2 504
TABLE 13: PIN IMPEDANCE (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Parameter
CI/O1
CIN1
LPIN2
Description
I/O Pin Capacitance
Input Capacitance
Pin Inductance
Test Condition
VI/O = 0V
VIN = 0V
Maximum
12 pF
12 pF
20 nH
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. Refer to PCI spec.
T13.4 504
TABLE 14: RELIABILITY CHARACTERISTICS
Minimum
Symbol
Parameter
Specification
Units
Test Method
NEND1
Endurance
10,000
Cycles
JEDEC Standard A117
TDR1
ILTH1
Data Retention
Latch Up
100
100 + IDD
Years
mA
JEDEC Standard A103
JEDEC Standard 78
T14.3 504
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 15: CLOCK TIMING PARAMETERS
Symbol
TCYC
THIGH
TLOW
-
-
Parameter
Min
CLK Cycle Time
30
CLK High Time
11
CLK Low Time
11
CLK Slew Rate (peak-to-peak)
1
RST# or INIT# Slew Rate
50
Max
4
Units
ns
ns
ns
V/ns
mV/ns
T15.1 504
0.5 VDD
0.4 VDD
0.3 VDD
Thigh
0.6 VDD
FIGURE 9: CLK WAVEFORM
Tcyc
Tlow
0.2 VDD
0.4 VDD p-to-p
(minimum)
504 ILL F27.0
©2001 Silicon Storage Technology, Inc.
20
S71161-06-000 9/01 504
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