SST49LF008C データシートの表示（PDF） - Silicon Storage Technology

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SST49LF008C

4 Mbit / 8 Mbit LPC Serial Flash

Silicon Storage Technology 

Advance Information

PIN DESCRIPTIONS

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

TABLE 1: PIN DESCRIPTION

Symbol Pin Name

LCLK

Clock

LAD[3:0] Address

and Data

LFRAME# Frame

RST#

INIT#

Reset

Initialize

ID[3:0]

Identification

Inputs

GPI[4:0]

General

Purpose

Inputs

TBL#

Top Block Lock

WP#/AAI Write Protect

WP#/AAI AAI Enable

RY/BY# Ready/Busy#

LD#

Load-Enable#

VDD

Power Supply

VSS

Ground

NC

No Connection

1. I=Input, O=Output

Type1

I

I/O

I

I

I

I

I

I

I

I

O

I

PWR

PWR

Interface

AAI LPC

XX

XX

XX

XX

XX

XX

X

X

X

X

X

X

XX

XX

N/A N/A

Functions

To accept a clock input from the control unit

To provide LPC bus information,

such as addresses and command Inputs/Outputs data.

To indicate the start of a data transfer operation;

also used to abort an LPC cycle in progress.

To reset the operation of the device

This is the second reset pin for in-system use.

This pin is internally combined with the RST# pin.

If this pin or RST# pin is driven low, identical operation is exhibited.

These four pins are part of the mechanism that allows multiple parts to be

attached to the same bus. The strapping of these pins is used to identify

the component. The boot device must have ID[3:0]=0000, all subsequent

devices should use sequential up-count strapping. These pins are inter-

nally pulled-down with a resistor between 20-100 KΩ. When in AAI mode,

these pins operate identically as in Firmware Memory cycles.

These individual inputs can be used for additional board flexibility.

The state of these pins can be read through LPC registers. These inputs

should be at their desired state before the start of the LPC clock cycle dur-

ing which the read is attempted, and should remain in place until the end

of the Read cycle. Unused GPI pins must not be floated.

GPI[2:4] are ignored when in AAI mode.

When low, prevents programming to the boot block sectors at top of device

memory. When TBL# is high it disables hardware write protection for the

top block sectors. This pin cannot be left unconnected.

TBL# setting is ignored when in AAI mode.

When low, prevents programming to all but the highest addressable block

(Boot Block). When WP# is high it disables hardware write protection for

these blocks. This pin cannot be left unconnected.

When set to the Supervoltage VH = 9V, configures the device to program

multiple bytes in AAI mode. When brought to VIL/VIH, returns device to

LPC mode.

Open drain output that indicates the device is ready to accept data in an

AAI mode, or that the internal cycle is complete.

Used in conjunction with LD# pin to switch between these two flag states.

Input pin which when low, indicates the host is loading data in an AAI pro-

gramming cycle. If LD# is high, the host signals the AAI interface that it is

terminating a command. LD# low/high switches the RY/BY# output from a

“buffer free” flag to a “programming complete” flag.

To provide power supply (3.0-3.6V)

Circuit ground (0V reference)

Unconnected pins.

T1.0 1292

©200 Silicon Storage Technology, Inc.

10

S71292-00-000

1/06

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