SST49LF020 データシートの表示（PDF） - Silicon Storage Technology

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SST49LF020

2 Megabit LPC Flash

Silicon Storage Technology 

To meet high density, surface mount requirements, the

SST49LF020 device is offered in 32-lead TSOP and 32-

lead PLCC packages. See Figures 1 and 2 for pinouts and

Table 2 for pin descriptions.

Mode Selection and Description

The SST49LF020 flash memory device operates in two

distinct interface modes: the LPC mode and the Parallel

Programming (PP) mode. The Mode pin is used to set the

interface mode selection. If the Mode pin is set to logic

High, the device is in PP mode; while if the Mode pin is set

Low, the device is in the LPC mode. The Mode selection

pin must be configured prior to device operation.

In LPC mode, the device is configured to its host using

standard LPC interface protocol. Communication

between Host and the SST49LF020 occurs via the 4-bit

I/O communication signals, LAD [3:0] and LFRAME#.

In PP mode, the device is programmed via an 11-bit

address and an 8-bit data I/O parallel signals. The address

inputs are multiplexed in row and column selected by con-

trol signal R/C# pin. The row addresses are mapped to the

higher internal addresses, and the column addresses are

mapped to the lower internal addresses. See Device Mem-

ory Map for address assignments.

LPC MODE

Device Operation

The LPC mode uses a 5-signal communication interface, a

4-bit address/data bus, LAD[3:0], and a control line,

LFRAME#, to control operations of the SST49LF020.

Cycle type operations such as Memory Read and Memory

Write are defined in Intel Low Pin Count Interface Specifi-

cation, Revision 1.0. JEDEC Standard SDP (Software

Data Protection) Program and Erase commands

sequences are incorporated into the standard LPC mem-

ory cycles. See Figure 8 through Figure 13 timing diagrams

for command sequences.

LPC operations are transmitted via the 4-bit Address/Data

bus (LAD[3:0]), and follow a particular sequence, depend-

ing on whether they are Read or Write operations. The

standard LPC memory cycle is defined in Table 13.

Both LPC Read and Write operations start in a similar way

as shown in Figures 6 and 7 timing diagrams. The host

(which is the term used here to describe the device driving

the memory) asserts LFRAME# for one or more clocks

and drives a start value on the LAD[3:0] bus.

2 Megabit LPC Flash

SST49LF020

Advance Information

At the beginning of an operation, the host may hold the

LFRAME# active for several clock cycles, and even change

the Start value. The LAD[3:0] bus is latched every rising

edge of the clock. On the cycle in which LFRAME# goes

inactive, the last latched value is taken as the Start value.

CE# must be asserted one cycle before the start cycle to

select the SST49LF020 for Read and Write operations.

Once the SST49LF020 identifies the operation as valid (a

start value of all zeros), it next expects a nibble that indicates

whether this is a memory read or program cycle. Once this

is received, the device is now ready for the Address and

Data cycles. For Program operation the Data cycle will fol-

low the Address cycle, and for Read operation TAR and

SYNC cycles occur between the Address and Data cycles.

At the end of every operation, the control of the bus must be

returned to the host by a 2 clock TAR cycle.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins

are provided for hardware write protection of device

memory in the SST49LF020. The TBL# pin is used to

write protect four boot sectors (16 KBytes) at the highest

memory address range. WP# pin write protects the

remaining sectors in the flash memory.

An active low signal at the TBL# pin prevents Program and

Erase operations of the top boot sectors. When TBL# pin is

held high, the write protection of the top boot sectors is dis-

abled. The WP# pin serves the same function for the

remaining sectors of the device memory. The TBL# and

WP# pins write protection functions operate independently

of one another.

Both TBL# and WP# pins must be set to their required

protection states prior to starting a Program or Erase

operation. A logic level change occurring at the TBL# or

WP# pin during a Program or Erase operation could

cause unpredictable results.

Reset

A VIL on INIT# or RST# pins initiates a device reset. INIT#

and RST# pins have same function internally. It is required

to drive INIT# or RST# pins low during a system reset to

ensure proper CPU initialization.

During a Read operation, driving INIT# or RST# pins low

deselects the device and places the output drivers,

LAD[3:0], in a high-impedance state. The reset signal must

be held low for a minimal duration of time TRSTP. A reset

latency will occur if a reset procedure is performed during a

Program or Erase operation. See Table 12, Reset Timing

Parameters, for more information. A device reset during an

active Program or Erase will abort the operation and mem-

©2001 Silicon Storage Technology, Inc.

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