SST49LF020 データシートの表示（PDF） - Silicon Storage Technology

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SST49LF020

2 Megabit LPC Flash

Silicon Storage Technology 

2 Megabit LPC Flash

SST49LF020

Advance Information

TABLE 2: PIN DESCRIPTION

Interface

Symbol Pin Name

Type1 PP LPC Functions

A10-A0

Address

IX

Inputs for low-order addresses during Read and Write operations. Addresses

are internally latched during a Write cycle. For the programming interface, these

addresses are latched by R/C# and share the same pins as the high-order

address inputs.

DQ7-DQ0 Data

I/O X

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle. The outputs are in tri-state when

OE# is high.

OE#

Output Enable I X

To gate the data output buffers.

WE#

Write Enable

IX

To control the Write operations.

MODE

Interface

Mode Select

I X X This pin determines which interface is operational. When held high, programmer

mode is enabled and when held low, LPC mode is enabled. This pin must be

setup at power-up or before return from reset and not change during device oper-

ation. This pin is internally pulled down with a resistor between 20-100KΩ.

INIT#

Initialize

I

X This is the second reset pin for in-system use. This pin is internally combined

with the RST# pin; If this pin or RST# pin is driven low, identical operation is

exhibited.

GPI[4:0] General

I

Purpose Inputs

X These individual inputs can be used for additional board flexibility. The state of

these pins can be read through LPC registers. These inputs should be at their

desired state before the start of the PCI clock cycle during which the read is

attempted, and should remain in place until the end of the Read cycle. Unused

GPI pins must not be floated.

TBL#

Top Block Lock I

X When low, prevents programming boot block sectors at top of memory. When

TBL# is high it disables hardware write protection for the top block sectors.

LAD[3:0] Address and

I/O

Data

X To provide LPC control signals, as well as addresses and Command

Inputs/Outputs data.

LCLK

Clock

I

X To provide a clock input to the control unit

LFRAME# Frame

I

X To indicate start of a data transfer operation; also used to abort an LPC cycle

in progress.

RST#

Reset

I X X To reset the operation of the device

WP#

Write Protect

I

X When low, prevents programming to all but the highest addressable top boot

blocks. When WP# is high it disables hardware write protection for these blocks.

R/C#

Row/Column

Select

IX

Select for the Programming interface, this pin determines whether the address

pins are pointing to the row addresses, or to the column addresses.

RES

Reserved

X These pins must be left unconnected.

VDD

Power Supply

I

X X To provide power supply (3.0-3.6V)

Vss

Ground

I X X Circuit ground (OV reference)

CE#

Chip Enable

I

X This signal must be asserted to select the device. When CE# is low, the device

is enabled. When CE# is high, the device is placed in low power standby mode.

NC

No Connection I X X Unconnected pins.

1. I=Input, O=Output

T2.3 526

©2001 Silicon Storage Technology, Inc.

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S71175-02-000 5/01 526

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