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ST62E62CD データシートの表示(PDF) - STMicroelectronics

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ST62E62CD Datasheet PDF : 72 Pages
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ST62T52CM-Auto ST62T62CM-Auto
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T52C and ST62T62C devices is low cost
members of the ST62xx 8-bit HCMOS family of mi-
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
core is surrounded by a number of on-chip periph-
erals.
The ST62E62C is the erasable EPROM version of
the ST62T62C device, which may be used to em-
ulate the ST62T52C and ST62T62C devices as
well as the ST6252C and ST6262B ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
Figure 1. Block Diagram
fined in the programmable option byte of the
OTP/EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T52C), an
8-bit A/D Converter with 4 analog inputs and a Dig-
ital Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
TEST/VPP
NMI
TEST
8-BIT
A/D CONVERTER
INTERRUPT
PROGRAM
MEMORY
1836 bytes OTP
(ST62T52C, T62C)
1836 bytes EPROM
(ST62E62C)
DATA ROM
USER
SELECTABLE
DATA RAM
128 Bytes
DATA EEPROM
64 Bytes
(ST62T62C/E62C)
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUPPLY
OSCILLATOR
RESET
VDD VSS OSCin OSCout RESET
PORT A
PORT B
PORT C
AUTORELOAD
TIMER
TIMER
PA4..PA5 / Ain
PB0, PB2..PB3 / 30 mA Sink
PB6 / ARTimin / 20 mA Sink
PB7 / ARTimout / 20 mA Sink
PC2..PC3 / Ain
DIGITAL
WATCHDOG
4/72

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