ST7032 データシートの表示（PDF） - Sitronix Technology Co., Ltd.
部品番号
コンポーネント説明
メーカー
ST7032 Datasheet PDF : 63 Pages
| |||
ST7032
n Pin Function
Name
Number
XRESET
1
RS
1
R/W
1
E
1
CSB
1
DB4 to DB7
4
DB0 to DB3
4
Ext
1
PSB
1
I/O Interfaced with
Function
External reset pin. Only if the power on reset used, the
I
MPU
XRESET pin must be fixed to VDD.
Low active.
Select registers.
0: Instruction register (for write)
I
MPU
Busy flag & address counter (for read)
1: Data register (for write and read)
Select read or write (In parallel mode).
I
MPU
0: Write
1: Read
Starts data read/write. (“E” must connect to “VDD” when
I
MPU
serial interface is selected.)
Chip select in parallel mode and serial interface (Low
I
MPU
active).When the CSB in falling edge state (in serial
interface), the shift register and the clock counter are reset.
Four high order bi-directional data bus pins. Used for data
transfer and receive between the MPU and the ST7032.
DB7 can be used as a busy flag. In serial interface mode
DB7 is SI (input data), DB6 is SCL (serial clock).
I/O
MPU
In I2C interface DB7 (SDA) is input data and DB6 (SCL) is
clock input.
SDA and SCL must connect to I2C bus (I2C bus is to connect
a resister between SDA/SCL and the power of I2C bus ).
Four low order bi-directional data bus pins. Used for data
I/O
MPU
transfer and receive between the MPU and the ST7032.
These pins are not used during 4-bit operation.
Extension instruction select:
0:enable extension instruction(add contrast/ICON/double
I
ITO option
height font/ extension instruction)
1:disable extension instruction(compatible to ST7066U, but
without 5x11dot font)
Interface selection
0:serial mode
I
MPU
(“E” must connect to “VDD” when serial mode is selected.)
1:parallel mode(4/8 bit)
In I2C interface PSB must connect to VDD
PSI2B
OPR1,
OPR2
PSB PSI2B
Interface
0
0
No use
1
I
ITO option
0
1
SI4
1
0
SI2 (I2C )
1
1
Parallel 68
Character generator select:
OPR1 OPR2
CGROM
CGRAM
0
0
240
8
2
I
ITO option
0
1
250
6
1
0
248
8
1
1
256
0
V1.4
7/61
2008/08/18
Share Link: 