ST7033 データシートの表示（PDF） - Sitronix Technology Co., Ltd.
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ST7033 Datasheet PDF : 39 Pages
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ST7033
7. FUNCTIONS DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
There is /CSB pin for chip selection. The ST7033 can interface with an MPU when /CSB is "L". When /CSB is “H”, the
internal shift register and the counter are reset.
Parallel / Serial Interface
ST7033 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial
interface is determined by PS [1:0] pin as shown in Table 1.
PS1 PS0 /CSB A0
State
H
H /CSB A0
8080-series parallel MPU interface
H
L /CSB A0
6800-series parallel MPU interface
L
H /CSB A0
4 Pin-SPI MPU interface
L
L /CSB " * "
3 Pin-SPI MPU interface
Table 1. Parallel/Serial Interface Mode
Parallel Interface
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1~PS0 as shown in
Table 2. The type of data transfer is determined by signals at A0, /RD (E) and /WR(R/W) as shown in Table 3.
PS1 PS0 /CSB A0 /RD (E) /WR (R/W) DB0 to DB7 MPU bus
H
H /CSB A0 /RD
/WR
DB0 to DB7 8080-series
H
L /CSB A0
E
R/W
DB0 to DB7 6800-series
Table 2. Microprocessor Selection for Parallel Interface
Common
A0
H
H
L
L
6800-series
E
R/W
H
H
H
L
H
H
H
L
8080-series
/RD
/WR
Description
L
H
Display data read out
H
L
Display data write
L
H
Register status read
H
L
Writes to internal register (instruction)
Table 3. Parallel Data Transfer
NOTE: By fixing /RD (E) pin at high (VDD1) in 6800-series interface mode, /CSB can be used as enable signal. In this case,
interface data is latched at the rising edge of /CSB and the access type is determined by signals on A0, /WR(R/W) just
same as 6800-series mode.
Ver 1.1
10/39
2009/07/17
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