ST72F321R9TA データシートの表示（PDF） - STMicroelectronics

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ST72F321R9TA

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C INTERFACE

STMicroelectronics 

ST72321

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

0058h

to

006Fh

Reserved Area (24 Bytes)

0070h

0071h

0072h

ADC

ADCCSR

ADCDRH

ADCDRL

Control/Status Register

Data High Register

Data Low Register

00h

R/W

00h

Read Only

00h

Read Only

0073h

0074h

0075h

0076h

0077h

PWMDCR3

PWMDCR2

PWMDCR1

PWMDCR0

PWMCR

PWM AR Timer Duty Cycle Register 3

PWM AR Timer Duty Cycle Register 2

PWM AR Timer Duty Cycle Register 1

PWM AR Timer Duty Cycle Register 0

PWM AR Timer Control Register

00h

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

0078h

PWM ART ARTCSR Auto-Reload Timer Control/Status Register

00h

R/W

0079h

ARTCAR Auto-Reload Timer Counter Access Register

00h

R/W

007Ah

ARTARR Auto-Reload Timer Auto-Reload Register

00h

R/W

007Bh

007Ch

007Dh

ARTICCSR AR Timer Input Capture Control/Status Reg.

00h

R/W

ARTICR1 AR Timer Input Capture Register 1

00h

Read Only

ARTICR2 AR Timer Input Capture Register 1

00h

Read Only

007Eh

007Fh

Reserved Area (2 Bytes)

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

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