STE2004SDIE2 データシートの表示（PDF） - STMicroelectronics

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STE2004SDIE2

102 x 65 single-chip LCD controller/driver

STMicroelectronics 

STE2004S

3

Circuit description

Circuit description

3.1

Supplies voltages and grounds

VDD2 supplies voltages to the internal voltage generator (see below). If the internal voltage

generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the

IC. VDD1 supply voltage could be different form VDD2.

VDD

2

≥

2-----⋅------V-----L---C-----D---

(n + 4)

+

200mV

3.2

Internal supply voltage generator

The IC has a fully integrated (no external capacitors required) charge pump for the liquid

crystal display (LCD) supply voltage generation. The multiplying factor can be programmed

to be: Auto, X5, X4, X3, X2, using the ’set CP multiplication’ command. If auto is set, the

multiplying factor is automatically selected to have the lowest current consumption in every

condition, allowing an input voltage that changes over time and a constant VLCD voltage.

The output voltage (VLCD) is tightly controlled through the VLCDSENSE pad. For this voltage,

eight different temperature coefficients (TC, rate of change with temperature) can be

programmed using the bits TC1, TC0, T2, T1, T0, to ensure there is no contrast degradation

over the LCD operating range.

An external supply could be connected to VLCD to supply the LCD without using the internal

generator. In such event the internal voltage generator must be programmed to zero (PRS =

[0;0], Vop = 0 - reset condition) and the charge pump (CP[0;0]) set to 5x or quto mode.

3.3

Oscillator

A fully integrated oscillator (requires no external components) is present to provide the clock

for the display system. When used the OSC pad must be connected to VDD1 pad. An

external oscillator could be used and fed into the OSC pin. If an external oscillator is used, it

must be always present when STE2004S is not in power down mode. An oscillator out is

provided on the OSCOUT Pad to cascade two or more drivers.

3.4

Master/slave mode

STE2004S supports the master slave working mode for both control logic and charge pump.

This function allows to drive matrix such as 204x65 or 102x130 using two synchronized

STE2004S and the internal charge pump of both devices.

If M/S is connected to VDD1, the driver is configured to work in master mode. When

STE2004S is in master mode, the Vsense_Slave pin is disabled and the VLCD value can be

controlled using Vop bits. The master time generator outputs the relevant timing references

on FR_OUT and OSC_OUT.

If M/S is connected to GND, the driver is configured to work in slave mode. When

STE2004S is in slave mode, the VLCD configuration set by Vop registers and the thermal

compensation slope set by TC register, are neglected. The VLCD value generated is equal

to the voltage value present on the Vsense_Slave pin so the slave configuration can follow

9/79

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