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STI5162 データシートの表示(PDF) - STMicroelectronics

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STI5162
ST-Microelectronics
STMicroelectronics ST-Microelectronics
STI5162 Datasheet PDF : 7 Pages
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STi5162
Description
1.3
Main features
Enhanced ST20 32-bit VL-RISC CPU
– 200-MHz, single cycle cache/4-Kbyte instruction cache, 4-Kbyte data cache,
4-Kbyte SRAM
Local memory interface
– up to 133 MHz, 16-bit wide SDR SDRAM,
– up to 166 MHz, 16-bit wide DDR SDRAM
Programmable Flash memory interface
– 3 separately configurable banks, 8/16-bits wide
– SRAM, peripheral, Flash, SFlash™ support
Demodulator compatible with I and Q or IF inputs for tuner interface
– wide range carrier tracking loop for offset recovery
– dual analog to digital conversion
– signal strength indicator dedicated ADC
– dual ΣΔ digital split AGC for RF and BB
Channel management
– NorDig Unified Specification (v1.0.2) capable
– dynamic fading compatible
– channel reception quality indicator
– out of guard interval echo synchronization
– impulsive noise rejection capable
– flexible fully-integrated digital channel filter with outstanding adjacent channel
rejection capability
Digital carrier, timing & symbol recovery loops
Decoding
– 2 K, 4 K, 8 K FFT length
– 5, 6, 7 and 8 MHz channel bandwidth
– 1/4, 1/8, 1/16, 1/32 guard interval length
– QPSK - 16 QAM - 64 QAM constellations
– hierarchical capability
– Viterbi soft decoder rate 1/2
– supports puncture rates 1/2, 2/3, 3/4, 5/6, 7/8
– Reed-Solomon decoder
– energy dispersal descrambler
Programmable transport interface (PTI)
– single transport stream input
– support for DVB transport streams
– integrated DVB, ICAM descramblers
MPEG-2 MP@ML video decoder
– fully programmable horizontal and vertical SRCs
Graphics and display
– 3 display planes
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