STHS4257A データシートの表示（PDF） - STMicroelectronics

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STHS4257A

IEEE 802.3af PoE Powered Device (PD) interface controller with integrated signature resistor

STMicroelectronics 

Summary description

Figure 1. Logic diagram

STHS4257A, STHS4257A1, STHS4257L, STHS4257L1

GND

SIGDISA(1)

RCLASS

STHS4257A/L

STHS4257A1/L1

PWRGD

VOUT

VIN

AI12214a

1. STHS4257A1 and STHS4257L1 devices only.

Table 2. Signal names

Pin

t(s) STHS4257A/L STHS4257A1/L1

uc 1, 3, 7

1, 3

rod 2

2

P 4

4

te 5

5

le 6

6

so —

7

b 8

8

Symbol

NC

RCLASS

VIN

VOUT

PWRGD

SIGDISA

GND

Description

No Connect

Classification pin

Negative return power line to PSE

Power Output (negative rail)

Power Good Output, open drain, active-low (referenced to VIN)

Signature Disable Input, internally pulled to VIN

Positive Power Supply; common input/output power rail

t(s) - O Figure 2. Pin connections (STHS4257A/L, top view)

uc NC

1

rod RCLASS

2

NC

3

lete P VIN

4

8

GND

7

NC

6

PWRGD

5

VOUT

AI12204b

Obso Figure 3. Pin connections (STHS4257A1/L1, top view)

NC

1

RCLASS

2

NC

3

VIN

4

8

GND

7

SIGDISA

6

PWRGD

5

VOUT

AI12205b

6/18

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