STK12C68-40M データシートの表示（PDF） - Unspecified
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STK12C68-40M Datasheet PDF : 10 Pages
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STK12C68-M
SOFTWARE STORE/RECALL CYCLE
(VCC = 5.0V ± 10%)d
SYMBOLS
NO.
Std.
Alt.
PARAMETER
STK12C68-40M
MIN MAX
STK12C68-45M
MIN MAX
STK12C68-55M
MIN MAX
UNITS
28
tAVAV
tRC
29
tELQZp
30
tAVELN
tAE
31
tELEHNq,r
tEP
32
tEHAXN
tEA
STORE/RECALL Initiation Cycle Time
Chip Enable to Output Inactive
Address Set-up to Chip Enable
Chip Enable Pulse Width
Chip Disable to Address Change
35
45
55
ns
85
85
85
ns
0
0
0
ns
25
35
45
ns
0
0
0
ns
Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence.
Note r: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end
of the low pulse, however the STORE or RECALL will still be initiated.
Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout.
Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-M performs a STORE or RECALL.
Note t: E must be used to clock in the address sequence for the Software STORE and RECALL cycles.
SOFTWARE STORE/RECALL CYCLE q,r,t
ADDRESS
E
30
tAVELN
28
tAVAV
ADDRESS #1
31
tELEHN
32
tEHAXN
28
tAVAV
ADDRESS #2
DQ(Data Out)
VALID
ADDRESS #6
23
tSTORE
22
tRECALL
29
tELQZ
VALID
HIGH IMPEDANCE
4-58
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