STK14C88-LF45TR データシートの表示（PDF） - Cypress Semiconductor
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STK14C88-LF45TR Datasheet PDF : 20 Pages
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STK14C88
nvSRAM Operation
Software Nonvolatile STORE
The STK14C88 has two separate modes of operation: SRAM
The STK14C88 software STORE cycle is initiated by executing
mode and nonvolatile mode. In SRAM mode, the memory
sequential E controlled read cycles from six specific address
operates as a standard fast static RAM. In nonvolatile mode,
locations. During the STORE cycle an erase of the previous
data is transferred from SRAM to nonvolatile elements (the
nonvolatile data is first performed, followed by a program of the
STORE operation) or from nonvolatile elements to SRAM (the
nonvolatile elements. The program operation copies the SRAM
RECALL operation). In this mode, SRAM functions are disabled. data into nonvolatile memory. When a STORE cycle is initiated,
Noise Considerations
further input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
The STK14C88 is a high speed memory and so must have a high
frequency bypass capacitor of approximately 0.1 F connected
between VCAP and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals helps to prevent noise problems.
SRAM Read
The STK14C88 performs a read cycle whenever E and G are
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence will be
s aborted and no STORE or RECALL takes place.
n To initiate the software STORE cycle, the following read
ig sequence must be performed:
1. Read address 0E38 (hex) Valid READ
s 2. Read address 31C7 (hex) Valid READ
De 3. Read address 03E0 (hex) Valid READ
low, and W and HSB are high. The address specified on pins
A0-14 determines which of the 32,768 data bytes are accessed.
w When the read is initiated by an address transition, the outputs
e are valid after a delay of tAVQV (Read cycle #1). If the read is
initiated by E or G, the outputs are valid at tELQV or at tGLQV,
N whichever is later (Read cycle #2). The data outputs repeatedly
r respond to address changes within the tAVQV access time
without the need for transitions on any control input pins, and
fo remain valid until another address change or until E or G is
brought high, or W or HSB is brought low.
ed SRAM Write
d A write cycle is performed whenever E and W are low, and HSB
n is high. The address inputs must be stable prior to entering the
e write cycle and must remain stable until either E or W goes high
at the end of the cycle. The data on the common I/O pins DQ0-7
m are written into the memory if it is valid tDVWH before the end of
a W controlled write or tDVEH before the end of an E controlled
m write.
o Keep G high during the entire write cycle to avoid data bus
c contention on common I/O lines. If G is left low, internal circuitry
e turns off the output buffers tWLQZ after W goes low.
R Power Up RECALL
ot During power up, or after any low power condition (VCAP <
VRESET), an internal RECALL request is latched. When VCAP
N again exceeds the sense voltage of VSWITCH, a RECALL cycle
is automatically initiated and takes tRESTORE to complete.
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled reads.
After the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. Use only read cycles
in the sequence, although it is not necessary that G be low for
the sequence to be valid. After the tSTORE cycle time is fulfilled,
the SRAM is again activated for read and write operation.
Software Nonvolatile RECALL
A software RECALL cycle is initiated with a sequence of read
operations in a manner similar to the software STORE initiation.
To initiate the RECALL cycle, the following sequence of E
controlled read operations must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and second, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation in no way alters the data in the nonvolatile elements.
If the STK14C88 is in a write state at the end of power up
The nonvolatile data can be recalled an unlimited number of
RECALL, the SRAM data will be corrupted. To avoid this, a 10
times.
KOhm resistor should be connected either between W and
system VCC or between E and system VCC.
AutoStore Mode
The STK14C88 can be powered in one of three modes.
During normal AutoStore operation, the STK14C88 draws
current from VCC to charge a capacitor connected to the VCAP
pin. This stored charge is used by the chip to perform a single
STORE operation. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part automatically disconnects the
VCAP pin from VCC and initiate a STORE operation.
Document Number: 001-52038 Rev. *C
Page 11 of 20
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