STK14C88-LF45TR データシートの表示（PDF） - Cypress Semiconductor
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STK14C88-LF45TR Datasheet PDF : 20 Pages
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STK14C88
SRAM Write Cycle #1 and #2
(VCC = 5.0V ± 10%)[4]
Symbols
NO.
#1
#2
Alt.
Parameter
STK14C88-25 STK14C88-35 STK14C88-45
Unit
Min Max Min Max Min Max
12 tAVAV
tAVAV
tWC Write Cycle Time
25
–
35
–
45
–
ns
13 tWLWH
tWLEH
tWP Write Pulse Width
20
–
25
–
30
–
ns
14 tELWH
tELEH
tCW Chip Enable to End of Write
20
–
25
–
30
–
ns
15 tDVWH
16 tWHDX
17 tAVWH
18 tAVWL
19 tWHAX
20 tWLQZ[8, 9]
21 tWHQX
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tDW Data Setup to End of Write
tDH Data Hold after End of Write
tAW Address Setup to End of Write
tAS Address Setup to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
10
0
20
0
0
–
5
–
–
–
–
–
10
–
12
–
15
0
–
0
s 25
–
30
n 0
–
0
ig 0
–
0
s –
13
–
De5
–
5
–
–
–
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
New ADDRESS
for E
ded W
en DATA IN
mm DATA OUT
Not Reco ADDRESS
Figure 6. SRAM Write Cycle 1: W Controlled [10, 11]
12
tAVAV
14
tELWH
19
tWHAX
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
13
tWHDX
21
tWHQX
Figure 7. SRAM Write Cycle 2: E Controlled [10, 11]
12
tAVAV
18
tAVEL
14
tELEH
19
tEHAX
E
W
DATA IN
17
tAVEH
13
tWLEH
15
tDVEH
DATA OUT
HIGH IMPEDANCE
Notes
9. If W is low when E goes low, the outputs remain in the high impedance state.
10. E or W must be VIH during address transitions.
11. HSB must be high during SRAM write cycles.
DATA VALID
Document Number: 001-52038 Rev. *C
16
tEHDX
Page 7 of 20
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