STK1743-D35I データシートの表示（PDF） - Unspecified

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STK1743-D35I

nvTime™ 8K x 8 AutoStore™ nvSRAM with Real-Time Clock

Unspecified 

STK1743

SOFTWARE MODE SELECTION

E

W

L

H

L

H

A12 - A0 (hex)

0000

1555

0AAA

1FFF

10F0

0F0F

0000

1555

0AAA

1FFF

10F0

0F0E

MODE

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile STORE

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile RECALL

I/O

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

NOTES

l

l

Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.

SOFTWARE CYCLES #1 & #2m, n

(VCC = 5.0V ± 10%)

SYMBOLS

NO.

#1

PARAMETER

STK1743-25

MIN

MAX

STK1743-35

MIN

MAX

STK1743-45

MIN

MAX

UNITS

27

tAVAV

STORE/RECALL Initiation Cycle Time

28

tAVELm

Address Set-up Time

29

tELEHm

Clock Pulse Width

30

tELAXg, m

Address Hold Time

31

tRECALL

RECALL Duration

25

35

45

ns

0

0

0

ns

20

25

30

ns

20

20

20

ns

20

20

20

µs

Note m: The software sequence is clocked with E controlled reads.

Note n: The six consecutive addresses must be in the order listed in the Software Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a

STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles.

SOFTWARE CYCLE: E Controlled

ADDRESS

27

tAVAV

ADDRESS #1

27

tAVAV

ADDRESS #6

28

tAVEL

29

tELEH

E

DQ (DATA OUT)

30

tELAX

DATA VALID

/ 23

31

tSTORE tRECALL

DATA VALID

HIGH IMPEDENCE

March 1999

7-6

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