STK673-011-E データシートの表示（PDF） - SANYO -> Panasonic
部品番号
コンポーネント説明
メーカー
STK673-011-E Datasheet PDF : 15 Pages
| |||
STK673-011-E
Notes On Use
(1) Input terminal use of 5V system
[RESET and Clock (timing of input signal upon rising of power supply)]
The driver is configured to include a 5V system logic section and a 24V MOSFETs section. The MOSFETs on both
VCC1 side and GND side are N-channels. Thus, the MOSFETs on the VCC1 side is provided with a charging pump
circuit for generating a voltage higher than that of VCC1. When a Low signal is input to a RESET terminal for
operating the RESET, the charging pump is stopped. After the release of the RESET (High input), it requires a period of
1.7ms to rise the charging pump. Accordingly, even when a Clock signal is input during the rising of the charging pump
circuit, the MOSFET cannot be operated. Such a timing needs to be taken into consideration for inputting a Clock signal.
An example of timing is shown in Figure 1.
Rising of 5V power supply
RESET signal input
Clock signal
> 10μs
> 1.7ms
ITF00809
Figure 1. Timing chart of RESET signal and Clock signal
When the RESET terminal switches from Low to High where a High period is 1.7ms or longer and the Clock input is
conducted in a Low state, each phase current of the motor is maintained at the following values.
Phase
Current in the case where the initial Clock signal is maintained
at Low level (Other than 2-3-phase TU excitation)
U phase
0
V phase
-87% of peak current during normal rotation
W phase
+87% of peak current during normal rotation
Refer to the timing charts for operations.
Current in the case where the initial Clock signal is maintained
at Low level (2-3-phase TU excitation)
0
-100% of peak current during normal rotation
+100% of peak current during normal rotation
[Clock]
Clock signals should be input under the following conditions so that all 9 types of excitation modes shown in the
Excitation Mode Table.
Input frequency range DC to 50kHz
Minimum pulse width 10μs
High level duty
40 to 60%
When Mode C is not used, it is an operation based on rising of the Clock and thus the above-mentioned condition of
high level duty is negligible. A minimum pulse width of 10μs or more allows excitation operation by Mode A and
Mode B. Since the operation is based on rising and falling of the Clock under the use of Mode C, it is most preferable to
set the high level duty to 50% so as to obtain uniform step-wise current widths.
[Mode A, Mode B, Mode C and TU]
These 4 terminals allow selection of excitation modes. For specific operations, refer to Excitation Mode Table and
Timing Charts.
No.A1137-6/15
Share Link: 