STV5346 データシートの表示（PDF） - STMicroelectronics

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STV5346

MONOCHIP TELETEXT DECODER WITH 8 INTEGRATED PAGES

STMicroelectronics 

STV5346 - STV5346/H - STV5346/T

FUNCTIONAL DESCRIPTION (continued)

III - I2C Bus Register Map (continued)

III.1 - Register Functions

Register

Function

Bit(s)

Description

SEL 11B (D0)

Selection of register 11B (D0 = 1) or 11A (D0 = 0)

R0

Address

00H

R11 adressing and

pin functions control

EVEN OFF (D2)

DISABLE ROLLING

HEADER

FREE RUNNING

PLL (D6)

Control of ODD/EVEN pin : EVEN signal output

(D2 = 0) or grounded (D2 = 1)

D4 = 1, Disable rolling header

D4 = 0, Normal operation

D6 = 0, PLL locks on line frequency

D6 = 1, to force free running mode

X/24 POSITION (D7)

T1 (D1)

0

0

1

1

T0 (D0)

0

1

0

1

D7 = 0, packet X/24 stored to chapter 4 to 7/row 20

D7 = 1, packet X/24 stored to chapter 0 to 3/row 24

Character display line control :

312/313 line MIX - mode with interlace

312/313 line TEXT - mode without interlace

312/312 line Terminal mode without interlace

External synchronization. SCS mode (scan field synchro)

R1

Address

01H

Operating mode

controls

TCS ON (D2)

DEW / FULLFIELD

(D3)

Master Mode (MA/SL Pin 2 = 0)

case POL Pin 4 = 0

D2 = 0, Pin 5 = VCS

D2 = 1, Pin 5 = TCS

Slave Mode (MA/SL Pin 2 = VDD)

No effect

Selection of field flyback mode or full channel mode

(D3 = 1) for recovering of Teletext data.

GHOST ROW

ENABLE (D4)

ACQUISITION

ON / OFF (D5)

Selection of ghost row mode (D4 = 1)

Control of acquisition operation (D5 = 0 enables

acquisition)

7 bits + parity or 8 bits Selection of received data format either 7 bits with parity

without parity (D6) (D6 = 0) or 8 bits without parity (D6 = 1).

R2

Address

02H

Addressing

information for

a page request

SC0, SC1, SC2

(D0, D1, D2)

TB (D3)

A0, A1 (D4, D5)

Address the first column of the on chip page request

RAM to be written.

Test bit equal to ”0” in the normal working mode.

Address a group of four consecutive pages currently

used for data acquisition.

A2 (D6)

Address of one of the two groups of four pages for

acquisition in normal mode.

R3

Address

03H

R4

Address

04H

Data relative to the

requested page

(see Table 3)

Selection of one

of eight pages

to display

PRD0 - PRD4

(D0 - D4)

A0, A1, A2

(D0, D1, D2)

Written data in the page request RAM, starting with the

columns addressed by SC0,SC1,SC2.

These 3 bits correspond to the logical states of the 3

address lines (A10, A11, A12) during memory read cycles.

R5

Address

05H

Display control for

normal operation

PON (D0, D1)

TEXT (D2, D3)

COR (D4, D5)

BKGND (D6, D7)

IN / OUT

Picture on (IN: D0, OUT: D1)

Text on (IN: D2, OUT: D3)

Contrast reduction on (IN: D4, OUT: D5)

Background color on (IN: D6, OUT: D7)

Enable inside/outside the box

R6

Address

06H

Display control for

news-flash subtitle

generation

See R5

See R5

11/21

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