STV7617DU データシートの表示（PDF） - STMicroelectronics
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STV7617DU Datasheet PDF : 17 Pages
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STV7617, STV7617D, STV7617U
BLOCK DIAGRAM
F/R
SEL
CLK
SIN (SOUT)
STB
BLK
HIZ
VCC
VCC
STV7617
SWITCH
65-BIT SHIFT REGISTER
P1
P65
S1
Q1 Q2
LATCH
S65
Q64Q65
VSSP
VPP
OUT1
VSSP
VPP
OUT64 OUT65
SOUT (SIN)
VCC
VSSS UB
VSSP
VSSL OG
VPP
CIRCUIT DESCRIPTION
The STV7617 contains all the logic and the power
circuits necessary to drive rows of a Plasma Dis-
play Panel (PDP). Data is shifted at each low to
high transition of the (CLK) shift clock. After 64 or
65 shifts (depending on SEL) the first bit presented
at (SIN) is available at the serial output (SOUT).
This output can be used to cascade several driv-
ers to perform any vertical resolution. CLK, STB,
SIN and SOUT inputs are Smith trigger inputs.
BLK and HIZ logical inputs are internally pulled to
level ”1”. The maximum frequency of the shift
clock is 8 MHz.
Shift register outputs (P1, ... P65) are transferred
from the shift register into the latch stage when the
latch input (STB) is at low level.
Table 1 : Output State Configuration
STB
BLK
HIZ
Output State
*
L
L High impedance
L
L
H
Inverted copy of input
data
H
L
H Data latched
*
H
L Low level
*
H
H High Level
Sustain current must not be sunk in the power out-
puts to VPP when the power supply is applied and
output state is in HIZ or at high state. VSSSUB and
VSSLOG must be connected as close as possible to
the logical reference ground of the application.
Table 2 : Shift Register Truth Table
F/R CLK SIN SOUT Comments
H
Rise
In
Out Forward Shift
H L or H In
Out Steady
L
Rise Out
In Reverse Shift
L L or H Out
In Steady
Table 3 : Power Output Configuration
SEL
F/R
Number of
Outpu ts
Comments
L
L
64
Out 1 is in Hi-Z mode (out-
puts 65 to 2 powered)
L
H
64
Out 65 is in Hi-Z mode (out-
puts 1 to 64 powered)
H
L
65
Out 65 to Out 1 powered
HH
65
Out 1 to Out 65 powered
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