STV7618 データシートの表示（PDF） - STMicroelectronics
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STV7618 Datasheet PDF : 16 Pages
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STV7618
6 - CIRCUIT DESCRIPTION
STV7618 includes all the logic and power circuits
necessary to drive column electrodes of a Plasma
Display Panel (P. D. P.). Binary values of each pix-
el of the displayed line are loaded into the shift reg-
ister by a 6 bits wide (A1 - A6) or 3 bits wide (A1 -
A3) data bus depending on the configuration of the
BS input pin. Data is shifted at each low to high
transition of the CLK clock.
The forward /reverse (F/R) input is used to select
the direction of the shift register.
The BS input is used to configure the shift register
either in 3 x 32 bits or in 6 x 16 bits.
In case of a 3bits arrangement, A1, A2 and A3
data bus input pins are used. The 3 shift registers
are loaded with 32 clock pulses. A4, A5 and A6
data bus input pins are at high impedance status.
The maximum frequency of the shift clock is
40MHz. This leads to an equivalent 240 MHz seri-
al shift register for a 6 x 16 bits arrangement.
When the STB signal is Low, data are transferred
from the shift register to the latch and power output
stages.
All the output data are kept memorised and held in
the latch stage when the latch input STB is pulled
high.
Vsssub and Vsslog must be connected as close as
possible to the logical reference ground of the ap-
plication.
STV7618 is supplied with a 5 volt power supply. All
the logic inputs can be driven either by 5V CMOS
logic, or by 3.3V CMOS logic.
Table 1: Shift register truth table
BS
F/R
X
L
X
L
X
H
X
H
H
X
L
X
Inp ut
CLK
rise
H or L
rise
H or L
X
X
Shift register function
Output Q
Forward shift
Steady
Reverse shift
Steady
3 bits shift register
6 bits shift register
Table 2: Power output truth table
Qn
STB
BLK
POC
Driver Output
Comments
X
X
L
X
X
X
H
L
all L
all H
Output at low level
Output at high level
X
H
H
H
Qn
Data latched
L
L
H
H
L
H
L
H
H
H
Data copied
Data copied
Qn+1 = A1, Qn+2 = A2, Qn+3 = A3, Qn+4 = A4, Qn+5 = A5, Qn+6 = A6, n = [0,6,12,18,...,90]
and BS = “L”
10/15
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