STV7733WPB3 データシートの表示（PDF） - STMicroelectronics
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STV7733WPB3 Datasheet PDF : 28 Pages
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Data bus configuration
4
Data bus configuration
STV7733
Note:
Below, Table 2 describes the position of the first data sampled by the first rising edge of the
SCLK clock. For the first configuration described in Table 2, that is, with input DIR = “H”,
data on the 2-bit bus DBA is sampled by the first SCLK clock pulse and appears on power
output OUT1. After 80 clock pulses, data on OUT1 will be shifted to OUT317 - on the
high-to-low transition of input /DL. Input /CS is the chip select.
Table 2. Data bus configuration
/CS DIR
Input
SCLK pulse number
Position
OUT1 OUT2 … OUT79 OUT80
Comment
DBA[1:2]
OUT
01
05
L
H
DBB[1:2]
OUT
02
06
DBC[1:2]
OUT
03
07
DBD[1:2]
OUT
04
08
DBA[1:2]
OUT
320
316
L
L
DBB[1:2]
OUT
319
315
DBC[1:2]
OUT
318
314
DBD[1:2]
OUT
317
313
313 317
314 318
Left/Right shift
315 319
316 320
08
04
07
03
Right/Left shift
06
02
05
01
Data is transferred from the shift register to a latch block and then on to power output stages
on the falling edge of input /DL, see Figure 2.
All output data is stored and held in the latch block on the rising edge of the input /DL, see
Figure 2.
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