ML53612 データシートの表示（PDF） - Oki Electric Industry

部品番号

コンポーネント説明

メーカー

ML53612

64-Channel Full Duplex H.100/H.110 CT Bus System Interface and Time-Slot Interchange

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s ML53612 s

4.7 Analog PLL

The analog PLL is used to create an internal 131.072 MHz clock locked to one of several reference fre-

quencies. The analog PLL reference signal is input on the APLL_CLKREF pin and should be a stable

clock typically ± 25 ppm. An external loop filter is required (see Figure 3).

CI

0.01 µF

R2

100Ω

R1

19 kΩ

APLL_PC

APLL_VCO

APLL_VSS

Figure 3. Analog PLL Loop Filter

4.8 Slave PLL

The slave PLL is used to generate all of the internal timing for the ML53612. Even when the ML53612 is

enabled as master, the slave PLL is still in operation. The slave PLL is a fast tracking digital PLL operat-

ing at 131.072 MHz.

The slave PLL can be configured to lock to one of the following sources:

• CT_C8_A and CT_FRAME_A

• CT_C8_B and CT_FRAME_B

• SCLK and FR_COMP

• C2 and FR_COMP

• L_CLK_0 and L_FS_0

• L_CLK_1 and L_FS_1

4.9 Master PLL

The master PLL is used to generate timing for the CT Bus. The master PLL is a digital PLL operating at

131.072 MHz. When operating as primary master the PLL can lock to one of two local network refer-

ences, or one of two CT Bus network references. These reference signals may be 8 kHz, 1.536 MHz, 1.544

MHz or 2.048 MHz. When operating as secondary master the PLL locks to the primary CT Bus master.

The master PLL can be configured to automatically switch from secondary to primary in the event of a

CT Bus timing error.

The master PLL can be configured to drive either the CT Bus "A" or "B" signals as well as all of the com-

patibility clocks defined in the H.100/H.110 Specifications.

When operating as the primary master, the PLL provides jitter attenuation with a cut-off frequency of

1.25 Hz and a roll-off of 20dB per decade. When operating as the secondary master, the PLL is fast track-

ing.

When operating as the primary master, the PLL has a lock range of ±488 ppm (minus the tolerance of

APLL_CLKREF source). The maximum lock time is 3s. Holdover stability is 0.06 ppm, resulting in a

frame slip rate of 42/day, assuming no drift in APLL_CLKREF source, exceeding the AT&T 62411 Stra-

Oki Semiconductor

9

Share Link: