SX1231H データシートの表示（PDF） - Semtech Corporation

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SX1231H

Low Power Integrated UHF Transceiver with On-Chip +20dBm PA

Semtech Corporation 

SX1231H

ADVANCED COMMUNICATIONS & SENSING

DATASHEET

This product datasheet contains a detailed description of the SX1231H performance and functionality. Please consult the

Semtech website for the latest updates or errata.

1. General Description

The SX1231H is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The

SX1231H's advanced features set, including state of the art packet engine greatly simplifies system design whilst the high

level of integration reduces the external BOM to a handful of passive decoupling and matching components. It is intended

for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bi-directional

RF links, and where stable and constant RF performance is required over the full operating range of the device down to

2.4V.

The SX1231H is intended for applications over a wide frequency range, including the 433 MHz and 868 MHz European

and the 902-928 MHz North American ISM bands. Coupled with a link budget in excess of 140 dB, the advanced system

features of the SX1231H include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature

sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU

requirements.

The SX1231H complies with both ETSI and FCC regulatory requirements and is available in a 5x 5 mm QFN 24 lead

package

1.1. Simplified Block Diagram

VBAT1&2

VR_ANA

VR_DIG

Power Distribution System

RC

Oscillator

RFIO

LNA

Σ/Δ

Single to

Mixers

Modulators

Differential

RESET

SPI

GND

VR_PA

PA_BOOST

PA0

Ramp &

Control

PA1&2

Tank

Inductor

Loop

Filter

Division by

2, 4 or 6

Frac-N PLL

Synthesizer

XO

32 MHz

RSSI

AFC

RXTX

DIO0

DIO1

DIO2

DIO3

DIO4

DIO5

Frequency Synthesis

Receiver Blocks

XTAL

GND

Transmitter Blocks

Control Blocks

Figure 1. Block Diagram

Primarily Analog

Primarily Digital

Rev 1 - Oct 2011

Page 8

www.semtech.com

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