SX1505I087TRT データシートの表示（PDF） - Semtech Corporation

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SX1505I087TRT

4/8/16 Channel GPIO with NINT and NRESET

Semtech Corporation 

ADVANCED COMMUNICATIONS & SENSING

SX1504/SX1505/SX1506

4/8/16 Channel GPIO

Symbol Description

tBUF

Bus free time between a

STOP and START condition

Cb

Capacitive load for each bus

line

Noise margin at the LOW

VnL

level for each connected

device (including hysteresis)

Noise margin at the HIGH

VnH level for each connected

device (including hysteresis)

Miscellaneous

RPULL

Programmable pull-up/down

resistors for IO[0-7]

tPLD

PLD propagation delay

Conditions

-

-

-

-

Min

Typ

1.3

-

-

-

0.1*VDDM -

0.2*VDDM -

-

-

60

VCC1,2 & VDDM = 5V

-

-

Max Unit

-

µs

400 pF

-

V

-

V

-

kΩ

25 ns

(1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND.

(2) All values referred to VIHMR min and VILM max levels.

(3) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to VIHMR min) to bridge the undefined region of

the falling edge of SCL.

(4) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

(5) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max+ tSU;DAT = 1000 + 250

= 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.

(6) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed.

Table 5 – Electrical Specifications

Rev 1 – 3rd Oct. 2008

9

www.semtech.com

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