NE5900 データシートの表示（PDF） - Philips Electronics
部品番号
コンポーネント説明
メーカー
NE5900 Datasheet PDF : 7 Pages
| |||
Philips Semiconductors
Call progress decoder
Product specification
NE5900
DC ELECTRICAL CHARACTERISTICS
VCC = +3.3V, TA = 25°C; unless otherwise stated.
SYMBOL
PARAMETER
VDD Power supply voltage
Quiescent current
Input threshold
Signal rejection
Low frequency2 rejection
High frequency2 rejection
VIH Logic 1 level
VIL
Logic 0 level
IIH
Logic 1 input current
IIL
Logic 0 input current
VIH Logic 1 input voltage
VIL
Logic 0 input voltage
VOL Logic 0 output voltage
VOH Logic 1 output voltage
IOZ
Tri-state leakage
Filter output gain
VREF
RREF
Filter frequency response
Input impedance
Reference voltage
Reference resistance
Envelope response time
NOTE:
1. 0dB = 0.775VRMS
2. By design; not tested.
TEST CONDITIONS
Pin 16
Pin 14 = VDD
Pin 5, 6 = 0V
As above with no output loads
Pin 1 level, frequency = 460Hz,
VDD = VREF Output Pin 13 = VDD
Pin 1 level, frequency = 300Hz,
VDD = VREF Output Pin 13 = 0V
Pin 1 frequency, 0dB max.,
VDC = VREF Output Pin 13 = 0V
Pin 1 frequency, 0dB max.,
VDC = VREF Output Pin 13 = 0V
Pins 6, 14
Pins 6, 14
Pins 3, 6, 14 = VDD
Pins 3, 6, 14 = 0V
Pin 3 External Clock In/XTAL
Pin 3 External Clock In/XTAL
ISINK = 1.6mA
Pins 7, 9, 10, 11, 12, 13
ISOURCE = 0.5mA
Pins 7, 9, 10, 11, 12, 13
VOUT = VDD or 0V
Pins 10, 11, 12, 13,
Pin 14 = 0V
Input Pin 1, 460Hz – 20dB,
VDC = VREF Output Pin 15,
RLOAD = 1MΩ
As above from 300Hz to 630Hz, refer-
enced to 460Hz
Pin 1, frequency = 460MHz
Pin 2, VDD = 5V
Pin 2
Time from removal or application of
460Hz – 20dB (VDC = VREF on Pin 1)
to response of Pin 13
MIN
4.5
800
2.0
0
-1.0
-1.0
VDD – 1
0
0
VDD – 0.4
-3.0
6.5
-1.0
1
2.4
LIMITS
TYP
5.0
2.0
-39
8.5
2.5
5
38
MAX
5.5
4.0
-35
-50
180
15
0.8
1.0
1.0
VDD
1.0
0.4
VDD
UNITS
V
mA
dB1
dB1
Hz
Hz
V
V
µA
µA
V
V
V
V
3.0
µA
10.5
dB
1.0
dBmo
MΩ
2.6
V
Ω
ms
The NE5900 uses the signal in the call progress tone passband and
the cadence of interrupt rate of the signal to determine which call
progress tone is present.
Figure 3 shows a detailed block diagram of the NE5900.
The signal input from the phone line is coupled through a 470kΩ
resistor which, together with two internal capacitors and an internal
resistor, form an anti-aliasing filter. This passive low pass filter
strongly rejects AM radio interference. Insertion loss is typically
1.5dB at 460Hz. The 470kΩ resistor also provides protection from
the transients. The input (Pin 1) DC voltage can be derived from
VREF (Pin 2) or allowed to self-bias through a series coupling
capacitor (10nF minimum).
Following this is a switched capacitor bandpass filter which accepts
call progress tones and inhibits tones not in the call progress band
of 300Hz to 630Hz. The bandpass limits are determined by the
input clock frequency of 3.58MHz. An on-board inverter between
Pins 3 and 4 can be used either as a crystal oscillator or as a buffer
for an external 3.58MHz clock signal. The switched capacitor filters
provide typical rejection of greater than 40dB for frequencies below
120Hz and above 1.6kHz.
The decoder responds to signals between 300Hz and 630Hz with a
threshold of -39dB typical (0dB = 0.775VRMS). The decoder will not
respond to any signal below -50dB or to tones up to 0dB which are
below 180Hz or above 800Hz. Dropouts of 20ms or bursts of only
20ms duration are ignored. A gap of 40ms or a valid tone of 40ms is
detected.
The buffered output of the switched capacitor filter is available at the
analog output, Pin 15. A logic output representing the detected
envelope of this signal is available at the envelope output, Pin 13.
1986 May 8
3
Share Link: 